characterization, modeling, and design of esd protection circuits

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196 Appendix A. Tracer User’s Manual Drain Current / amps/µm fixed num = 1 type=voltage value=0.0 record = no fixed num = 2 type=voltage value=-0.5 record = yes fixed num = 4 type=voltage value=0.0 record = no control num=3 begin=0.0 initstep=0.2 control=imax end=4.1e-4 solve first=load sim=pisc option verbose=no itlim=30 turnpts=yes freq=9 Fig. A.70 The trace file, mesvg.5.tra, for the GaAs MESFET example. Drain Voltage / volts Fig. A.71 Drain current vs. drain voltage for the GaAs MESFET example.
A.9. Examples 197 #Soln #Vctrl Ictrl I2 1 0.000000e+00 1.903203e-16 -4.790550e-16 2 2.000000e-01 4.411067e-05 -1.166555e-15 3 6.000000e-01 1.233240e-04 -2.412571e-15 4 1.400000e+00 1.985247e-04 -3.623966e-15 5 3.000000e+00 2.104332e-04 -3.936303e-15 6 4.600000e+00 2.155307e-04 -4.374722e-13 7 6.200000e+00 2.189477e-04 -2.059647e-11 8 7.000000e+00 2.202971e-04 -6.990150e-11 *9 7.800000e+00 2.214088e-04 -1.707327e-10 10 8.600000e+00 2.224028e-04 -3.638914e-10 11 9.400000e+00 2.232137e-04 -6.557824e-10 12 1.020000e+01 2.238725e-04 -1.043467e-09 13 1.180000e+01 2.249711e-04 -2.208417e-09 14 1.227965e+01 2.252584e-04 -2.671811e-09 15 1.258651e+01 2.254261e-04 -2.980391e-09 16 1.290104e+01 2.255882e-04 -3.308354e-09 17 1.354587e+01 2.258872e-04 -3.995203e-09 *18 1.441648e+01 2.262760e-04 -5.076190e-09 19 1.517061e+01 2.266211e-04 -5.076190e-09 20 1.818697e+01 2.280737e-04 -1.389891e-08 21 3.025183e+01 2.340778e-04 -1.841648e-07 22 3.326644e+01 2.357641e-04 -3.360147e-07 23 4.526743e+01 2.472668e-04 -2.984657e-06 24 4.787346e+01 2.524107e-04 -4.783998e-06 25 5.085805e+01 2.612441e-04 -4.783998e-06 26 5.436859e+01 2.808594e-04 -1.633647e-05 *27 5.639889e+01 3.073427e-04 -2.612463e-05 28 5.729060e+01 3.385567e-04 -3.460666e-05 *29 5.719992e+01 3.725458e-04 -3.844234e-05 30 5.586886e+01 4.090192e-04 -3.611460e-05 31 5.534786e+01 4.193991e-04 -3.517154e-05 Fig. A.72 The output file, mesvg.5.out, for the GaAs MESFET example.
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CHARACTERIZATION, MODELING, AND DES
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Abstract For more than 20 years, su
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Acknowledgments This work could not
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Contents Abstract iii Acknowledgmen
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6 Conclusion 165 6.1 Contributions
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List of Figures 1.1 ESD protection
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3.32 Simulated 1/∆T vs. time and
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A.65 The output file, bvceo.out, fo
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Chapter 1 Introduction Electrostati
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1.1. ESD in the Integrated Circuit
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1.2. Characterizing ESD in Integrat
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1.3. Protecting Integrated Circuits
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1.4. Numerical Simulation 9 simulat
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1.5. Design Methodology 11 process.
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1.6. Outline and Contributions 13 A
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Chapter 2 ESD Circuit Characterizat
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2.1. Classical ESD Characterization
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2.2. Transmission Line Pulsing 19 i
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2.2. Transmission Line Pulsing 21 (
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2.2. Transmission Line Pulsing 23 (
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2.2. Transmission Line Pulsing 25 I
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2.2. Transmission Line Pulsing 27 I
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2.2. Transmission Line Pulsing 29 E
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2.2. Transmission Line Pulsing 31 w
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2.2. Transmission Line Pulsing 33 a
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2.2. Transmission Line Pulsing 35 F
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2.3. Overview of Protection Circuit
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2.4. Dependence of Critical MOSFET
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2.4. Dependence of Critical MOSFET
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2.5. Design Methodology 49 the subs
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2.5. Design Methodology 51 The perf
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2.5. Design Methodology 53 enter se
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Chapter 3 Simulation: Methods and A
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3.1. Lattice Temperature and Temper
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3.2. Curve Tracing 65 line (c) in F
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3.3. Mixed Mode Simulation 67 x n-1
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3.3. Mixed Mode Simulation 69 V c C
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3.4. Previous ESD Applications 71 v
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3.4. Previous ESD Applications 73 I
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3.5. Extraction of MOSFET I-V Param
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3.6. Extraction of MOSFET Pf vs. tf
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3.7. Simulation of Dielectric Failu
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Chapter 4 Simulation: Calibration a
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4.1. Calibration Procedure 97 and t
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4.1. Calibration Procedure 99 conta
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4.1. Calibration Procedure 101 4.40
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4.1. Calibration Procedure 103 Afte
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4.1. Calibration Procedure 105 past
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4.1. Calibration Procedure 107 whic
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4.1. Calibration Procedure 109 simu
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4.1. Calibration Procedure 111 (a)
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4.1. Calibration Procedure 113 wher
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4.1. Calibration Procedure 115 peri
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4.1. Calibration Procedure 117 simu
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4.1. Calibration Procedure 119 volt
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4.2. MOSFET Snapback I-V Results 12
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4.2. MOSFET Snapback I-V Results 12
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4.3. Device Failure Results 125 V t
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4.3. Device Failure Results 127 alr
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4.3. Device Failure Results 129 act
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4.3. Device Failure Results 131 (a)
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4.3. Device Failure Results 133 (a)
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4.4. Design Example 135 reached, th
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4.4. Design Example 137 Using value
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Chapter 5 Design and Optimization o
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5.1. Methodology 141 5.1 Methodolog
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5.1. Methodology 143 W L DGS SGS Co
Page 161 and 162: 5.1. Methodology 145 reaches its pe
Page 163 and 164: 5.1. Methodology 147 the same withs
Page 165 and 166: 5.1. Methodology 149 various respon
Page 167 and 168: 5.1. Methodology 151 needed to desc
Page 169 and 170: 5.1. Methodology 153 The actual pat
Page 171 and 172: 5.2. Application 155 To determine h
Page 173 and 174: 5.3. Analysis 157 are flat, a direc
Page 175 and 176: 5.3. Analysis 159 assumed to be iso
Page 177 and 178: 5.4. Optimization 161 Qualitatively
Page 179 and 180: 5.5. Summary of Design Methodology
Page 181 and 182: Chapter 6 Conclusion In the integra
Page 183 and 184: 6.1. Contributions 167 TLP was show
Page 185 and 186: 6.2. Future Work 169 most ESD quali
Page 187 and 188: 6.2. Future Work 171 Significant wo
Page 189 and 190: Appendix A Tracer User’s Manual S
Page 191 and 192: A.3. CONTROL Card 175 A.3 CONTROL C
Page 193 and 194: A.4. FIXED Card 177 A.4 FIXED Card
Page 195 and 196: A.5. OPTION Card 179 • DAMP is a
Page 197 and 198: A.5. OPTION Card 181 A.5.4 Examples
Page 199 and 200: A.6. SOLVE Card 183 if the voltage
Page 201 and 202: A.7. Input Deck Specifications 185
Page 203 and 204: A.9. Examples 187 column contains c
Page 205 and 206: A.9. Examples 189 fixed num = 1 typ
Page 207 and 208: A.9. Examples 191 Collector Current
Page 209 and 210: A.9. Examples 193 title mes.pis mes
Page 211: A.9. Examples 195 simulator to use.
Page 215 and 216: Bibliography [1] T.J. Green and W.K
Page 217 and 218: Bibliography 201 [20] C. Duvvury, R
Page 219 and 220: Bibliography 203 [42] S.M. Sze, Phy
Page 221 and 222: Bibliography 205 [63] R. van Overst
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