characterization, modeling, and design of esd protection circuits

34 Chapter 2. ESD Circuit Characterization and Design Issues
log(I leak / A)
-3
-6
-9
-12
0 It1 1
Idev / A
It2 2
Fig. 2.13 Qualitative plot of device leakage evolution vs. stress-current
level of a TLP experiment. Transitions are evident at the
snapback and second-breakdown points.
drain-substrate junction, and/or a rupture of the gate oxide. In addition to this transition,
sudden increases in leakage from the pA to the nA range have been observed when the
device enters snapback [4]. Such a leakage evolution is depicted in Fig. 2.13 by plotting
leakage current vs. the device current of the previous TLP stress. Non-catastrophic
leakage (also called low-level leakage or soft failure) may be due to a small hot spot
forming just before the device snaps back, to a small filament in the gate oxide formed by
dielectric stress, or to hot-carrier trapping in the gate oxide which could induce a small
channel region by shifting the threshold voltage below zero (for an NMOS device).
Although the protection circuit still functions after a low-level stress, the increased
leakage may be a signature of a latent failure, i.e., a reduction in lifetime of the circuit due
to a “soft” ESD stress. Latent failure is a topic which merits further investigation, and the
monitoring of leakage current during stepped TLP stresses is a powerful way to study the
phenomenon.