characterization, modeling, and design of esd protection circuits

3.7. Simulation of Dielectric Failure and Latent ESD Damage 87
E max (10 6 V/cm) and V d (V)
24
20
16
12
8
4
0
0
+
V in
-
50Ω
50Ω
V d
E max
1.0 2.0 3.0 4.0
time / ns
Fig. 3.34 The maximum electric field in the gate oxide (E max , in MV/cm) of an
ESD-protection MOSFET subjected to a square pulse with a 3ns rise time
is plotted vs. time. As seen from the plot of the input voltage at the drain
of the device, V d , the reduction in E max is due to the device snapping back
at 1.2ns.
injection of charge into the oxide and high electric-field stress across the oxide (these are
not necessarily mutually exclusive). The simplest analysis of dielectric stress during ESD
involves recording the voltage across the gate oxide or the maximum electric field in the
oxide of the protection transistor for each solution in a transient or steady-state snapback
simulation. The device simulator does not report such voltage and electric-field
information directly, but the desired information can be extracted from files containing the
2D potential and electric-field profiles saved from each solution. Fig. 3.34 shows a plot of
the simulated maximum electric field vs. time in the 100Å-thick oxide of a protection
MOSFET subject to a square-wave pulse with a 3ns rise time. The simulator was
instructed to save the solution data for each time point, and the location and value of the
maximum electric field in the device were then automatically extracted from each solution
using a simple C program. Fig. 3.34 shows that the maximum electric field peaks at a
V d
5.0