characterization, modeling, and design of esd protection circuits

More documents

Recommendations

Info

50 Chapter 2. ESD Circuit Characterization and Design Issues Bond pad PMOS NMOS V CC V SS Input Fig. 2.20 Circuit diagram of CMOS input protection using multifinger structures. variations in gate length, gate width, and contact-to-gate spacing as well as devices with and without LDD, with and without silicidation, and thin-gate and thick-gate (field) structures. On each test tile there is a common p-well or substrate (VSS ) pad for the NMOS devices and a common n-well (VCC ) pad for the PMOS devices, but all devices have separate drain, source, and gate contacts to avoid destroying all devices when one device is overstressed. After processing, wafers are diced and the test-tile pads are wire bonded to pins of 24-pin or 28-pin dual in-line packages (DIPs). Gate resistance was not included in the layout of the structures, but a ceramic or chip resistor can be connected externally during testing to investigate gate bouncing. It is debatable whether this lumpedresistor approach accurately represents the use of any type of resistance which can be laid out, and future test tiles may have to include on-chip gate resistors. . . . . . . In theory, the simplest way to optimize a device is to create an n-dimensional design space, where n is the number of parameters which can be varied, i.e., gate length, gate width, contact-to-gate spacing, etc., and then test all of these devices and note which one performs the best. This procedure would require an impractical number--hundreds or thousands--of devices unless we use a statistical method such as that discussed in Chapter 5. Our approach in this section is to create separate one-dimensional variations of the layout parameters described in the previous section and extract a quantitative dependence of the TLP I-V points as well as HBM and CDM failure thresholds on these parameters. Given these dependences, one or more of the layout parameters can be set to yield optimal device characteristics for robust ESD protection.
2.5. Design Methodology 51 The performance of a single protection device is simple to define using the HBM or CDM test because the only characteristic of robustness is the maximum input voltage the device can withstand before the leakage current becomes too high. With TLP analysis, on the other hand, there are several considerations. To prevent dielectric breakdown of the thin input gates or of the thin gate of the protection MOSFET itself, the drain voltage should not exceed the dielectric breakdown threshold, which is about 8V for a 100Å oxide. This means that Vt1 should not exceed this value during initial turn-on, and Vsb and Rsb should be low enough that the drain voltage does not move out past the dielectric threshold while in the snapback mode (refer to Fig. 2.6). As mentioned in Section 2.3, there is a time dependence of dielectric failure, so it may be safe for Vt1 to exceed a steady-state breakdown level as long as the device turns on quickly enough. The MOSFET snapback process occurs on the order of 1ns, so the device should be able to follow any ESD input and clamp it successfully unless the rise time of the pulse is less than 1ns, which may be the case for a CDM stress. Vt1 should be as low as possible to minimize the chances of dielectric failure and the turn-on time, but it must remain above normal operating voltages so that it does not interfere with the operation of the IC. From the previous section, we expect the gate length and gate-bounce resistance to have the largest effect on Vt1 and the trigger time, t1 . To maximize the thermal failure threshold of a single device, the second breakdown current, It2 , or the power to failure, Pf , should be maximized across a range of time to failure, tf . Since Pf is the product of It2 and Vt2 , it appears that Vt2 should also be maximized to raise the Pf vs. tf curve. However, as just discussed the device voltage should not exceed the dielectric breakdown voltage. Also, if a technique such as increasing the contact-to-gate spacing is used to increase Rsb and thus increase Vt2 for the same It2 , the device has a higher failure power, but the failure current is the same because the extra power is dissipated in the resistance, not in the high J ⋅ E region, so the device is not really providing any more protection than before. Thus, it has been suggested [24] that an If vs. tf curve is just as valid, if not more valid, for characterizing the thermal robustness of a protection device. Design of a device should focus on maximizing It2 by making the device as wide as possible (within the constraints of the available ESD circuit area), blocking the shallow LDD diffusion, masking silicide deposition, and noting any secondorder dependence of It2 on gate length and contact-to-gate spacing.
Page 1 and 2:
CHARACTERIZATION, MODELING, AND DES
Page 3 and 4:
Abstract For more than 20 years, su
Page 5 and 6:
Acknowledgments This work could not
Page 7 and 8:
Contents Abstract iii Acknowledgmen
Page 9 and 10:
6 Conclusion 165 6.1 Contributions
Page 11 and 12:
List of Figures 1.1 ESD protection
Page 13 and 14:
3.32 Simulated 1/∆T vs. time and
Page 15 and 16: A.65 The output file, bvceo.out, fo
Page 17 and 18: Chapter 1 Introduction Electrostati
Page 19 and 20: 1.1. ESD in the Integrated Circuit
Page 21 and 22: 1.2. Characterizing ESD in Integrat
Page 23 and 24: 1.3. Protecting Integrated Circuits
Page 25 and 26: 1.4. Numerical Simulation 9 simulat
Page 27 and 28: 1.5. Design Methodology 11 process.
Page 29 and 30: 1.6. Outline and Contributions 13 A
Page 31 and 32: Chapter 2 ESD Circuit Characterizat
Page 33 and 34: 2.1. Classical ESD Characterization
Page 35 and 36: 2.2. Transmission Line Pulsing 19 i
Page 37 and 38: 2.2. Transmission Line Pulsing 21 (
Page 39 and 40: 2.2. Transmission Line Pulsing 23 (
Page 41 and 42: 2.2. Transmission Line Pulsing 25 I
Page 43 and 44: 2.2. Transmission Line Pulsing 27 I
Page 45 and 46: 2.2. Transmission Line Pulsing 29 E
Page 47 and 48: 2.2. Transmission Line Pulsing 31 w
Page 49 and 50: 2.2. Transmission Line Pulsing 33 a
Page 51 and 52: 2.2. Transmission Line Pulsing 35 F
Page 53 and 54: 2.3. Overview of Protection Circuit
Page 61 and 62: 2.4. Dependence of Critical MOSFET
Page 63 and 64: 2.4. Dependence of Critical MOSFET
Page 65: 2.5. Design Methodology 49 the subs
Page 69 and 70: 2.5. Design Methodology 53 enter se
Page 71 and 72: Chapter 3 Simulation: Methods and A
Page 73 and 74: 3.1. Lattice Temperature and Temper
Page 81 and 82: 3.2. Curve Tracing 65 line (c) in F
Page 83 and 84: 3.3. Mixed Mode Simulation 67 x n-1
Page 85 and 86: 3.3. Mixed Mode Simulation 69 V c C
Page 87 and 88: 3.4. Previous ESD Applications 71 v
Page 89 and 90: 3.4. Previous ESD Applications 73 I
Page 91 and 92: 3.5. Extraction of MOSFET I-V Param
Page 93 and 94: 3.6. Extraction of MOSFET Pf vs. tf
Page 103 and 104: 3.7. Simulation of Dielectric Failu
Page 111 and 112: Chapter 4 Simulation: Calibration a
Page 113 and 114: 4.1. Calibration Procedure 97 and t
Page 115 and 116: 4.1. Calibration Procedure 99 conta
Page 117 and 118:
4.1. Calibration Procedure 101 4.40
Page 119 and 120:
4.1. Calibration Procedure 103 Afte
Page 121 and 122:
4.1. Calibration Procedure 105 past
Page 123 and 124:
4.1. Calibration Procedure 107 whic
Page 125 and 126:
4.1. Calibration Procedure 109 simu
Page 127 and 128:
4.1. Calibration Procedure 111 (a)
Page 129 and 130:
4.1. Calibration Procedure 113 wher
Page 131 and 132:
4.1. Calibration Procedure 115 peri
Page 133 and 134:
4.1. Calibration Procedure 117 simu
Page 135 and 136:
4.1. Calibration Procedure 119 volt
Page 137 and 138:
4.2. MOSFET Snapback I-V Results 12
Page 139 and 140:
4.2. MOSFET Snapback I-V Results 12
Page 141 and 142:
4.3. Device Failure Results 125 V t
Page 143 and 144:
4.3. Device Failure Results 127 alr
Page 145 and 146:
4.3. Device Failure Results 129 act
Page 147 and 148:
4.3. Device Failure Results 131 (a)
Page 149 and 150:
4.3. Device Failure Results 133 (a)
Page 151 and 152:
4.4. Design Example 135 reached, th
Page 153 and 154:
4.4. Design Example 137 Using value
Page 155 and 156:
Chapter 5 Design and Optimization o
Page 157 and 158:
5.1. Methodology 141 5.1 Methodolog
Page 159 and 160:
5.1. Methodology 143 W L DGS SGS Co
Page 161 and 162:
5.1. Methodology 145 reaches its pe
Page 163 and 164:
5.1. Methodology 147 the same withs
Page 165 and 166:
5.1. Methodology 149 various respon
Page 167 and 168:
5.1. Methodology 151 needed to desc
Page 169 and 170:
5.1. Methodology 153 The actual pat
Page 171 and 172:
5.2. Application 155 To determine h
Page 173 and 174:
5.3. Analysis 157 are flat, a direc
Page 175 and 176:
5.3. Analysis 159 assumed to be iso
Page 177 and 178:
5.4. Optimization 161 Qualitatively
Page 179 and 180:
5.5. Summary of Design Methodology
Page 181 and 182:
Chapter 6 Conclusion In the integra
Page 183 and 184:
6.1. Contributions 167 TLP was show
Page 185 and 186:
6.2. Future Work 169 most ESD quali
Page 187 and 188:
6.2. Future Work 171 Significant wo
Page 189 and 190:
Appendix A Tracer User’s Manual S
Page 191 and 192:
A.3. CONTROL Card 175 A.3 CONTROL C
Page 193 and 194:
A.4. FIXED Card 177 A.4 FIXED Card
Page 195 and 196:
A.5. OPTION Card 179 • DAMP is a
Page 197 and 198:
A.5. OPTION Card 181 A.5.4 Examples
Page 199 and 200:
A.6. SOLVE Card 183 if the voltage
Page 201 and 202:
A.7. Input Deck Specifications 185
Page 203 and 204:
A.9. Examples 187 column contains c
Page 205 and 206:
A.9. Examples 189 fixed num = 1 typ
Page 207 and 208:
A.9. Examples 191 Collector Current
Page 209 and 210:
A.9. Examples 193 title mes.pis mes
Page 211 and 212:
A.9. Examples 195 simulator to use.
Page 213 and 214:
A.9. Examples 197 #Soln #Vctrl Ictr
Page 215 and 216:
Bibliography [1] T.J. Green and W.K
Page 217 and 218:
Bibliography 201 [20] C. Duvvury, R
Page 219 and 220:
Bibliography 203 [42] S.M. Sze, Phy
Page 221 and 222:
Bibliography 205 [63] R. van Overst
show all

characterization, modeling, and design of esd protection circuits

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?