characterization, modeling, and design of esd protection circuits

3.7. Simulation of Dielectric Failure and Latent ESD Damage 93
relatively small area of high temperature with no signs of second breakdown such as a
drop in the device voltage or increase in device current. As an example, a transient
simulation of a µm MOSFET stressed with a very high (120V), brief (3ns) ESD
pulse was run and the solutions were saved for each time point. Using a C program, the
temperature profile data was read from the solution file for the time coinciding with
maximum device temperature and then used to calculate points along constanttemperature
contours, shown in Fig. 3.37. Notice that the smallest contour contains the
area in which the temperature is greater than 1700K, demonstrating that melting may
occur in a small spot but should not be widespread. This spot is located near the surface at
the drain-LDD n + 50 ⁄ 0.5
/n junction. Combining the temperature data with the 2D doping-profile
data, a contour was also calculated within which the intrinsic carrier concentration, ni (T),
is greater than the background doping level (Fig. 3.38). Recall that one of the assumed
Depth / µm
0.0
0.1
0.2
0.3
0.4
Source
Gate
Substrate
n i > doping
Junction
0.0 0.4 0.8 1.2 1.6
Length / µm
Drain
Fig. 3.38 A contour within which the intrinsic carrier concentration, n i , is greater
than the background doping level is drawn for a simulation structure at
the time of peak ESD stress. Lines are also drawn marking the source and
drain junctions of the structure, which is not plotted to scale.