characterization, modeling, and design of esd protection circuits

26 Chapter 2. ESD Circuit Characterization and Design Issues
log(I device / amps)
V sb
1/R sb
V device / volts
V t2 , I t2
Second snapback
V t1 , I t1
Fig. 2.7 Depiction of second snapback in a qualitative transient I-V
curve for an NMOS transistor subjected to a positive ESD pulse.
layer in the lateral parasitic bipolar transistor (the effect of the source LDD region will be
ignored here). Since the thin epi layer makes second snapback possible in the bipolar
transistor, the LDD region could lead to a second snapback in the I-V curve, as depicted in
Fig. 2.7. However, the current level required to trigger second snapback may be higher
than the current which triggers thermal runaway and thus second snapback would not be
observed.
In stepping through a transient I-V curve with transmission-line pulsing, a curve much
like the one in Fig. 2.6a is generated. For initial pulses the device voltage closely follows
the input voltage because the device current is very low (Fig. 2.8). Note that the rise time
of the device voltage, which is a function of the equipment setup and is independent of the
pulse height, is about 3ns. If the resolution of the measurement is high enough, finite
current values can be recorded as the device voltage nears the trigger point Vt1 . When the
input voltage exceeds Vt1 , the device voltage will drop to the snapback level. With a highresolution
oscilloscope the initial rise of the device voltage and subsequent drop to the
snapback level can be captured as shown in Fig. 2.9. Beyond this point large steps in input
voltage are needed to raise the device voltage because significant device current is now