characterization, modeling, and design of esd protection circuits

92 Chapter 3. Simulation: Methods and Applications
breakdown. Simulations of the same ESD stresses and devices could be run on calibrated
2D structures and the resulting levels of gate current could be compared to the measured
change in characteristics to determine any correlation between simulated gate current and
measured oxide degradation.
In addition to dielectric damage, latent failures may also be caused by local heating, as
suggested by Kuper et al. [4]. Experimentally, latent thermal failures may be identified by
the measurement of low-level (sub-microamp) leakage after a moderate ESD stress or
during the evolution of a transmission-line pulsing experiment. Hypothetically, if a
localized hot spot developed at the drain-substrate junction during the stress, the low-level
leakage could be attributed to a resistive filament formed by the localized silicon melting.
Such a filament would act as a high resistance in parallel with the junction diode and thus
the device would become leaky. In a simulation, the latent “failure signature” would be a
Depth / µm
0.0
0.1
0.2
0.3
0.4
Source
Gate
T = 700K
T = 500K
Junction
0.0 0.4 0.8 1.2 1.6
Length / µm
Drain
Fig. 3.37 A constant-temperature contour is plotted for every 200K increment in
temperature for a simulation structure at the time of peak ESD stress.
Lines are also drawn marking the source and drain junctions of the
structure, which is not plotted to scale.
...
Substrate