characterization, modeling, and design of esd protection circuits

152 Chapter 5. Design and Optimization of ESD Protection Transistor Layout
One final modeling issue to consider is that since average values of withstand current or
voltage are used to develop the ESD circuit model, the model predicts the average HBM
withstand voltage of an actual protection circuit in an IC. However, when an IC is
subjected to the reliability qualification process, a limited number of parts are tested at one
or more voltages for various pin combinations, and the withstand voltage is taken to be the
highest stress voltage for which all of the sample parts pass. Furthermore, multiple pins
are tested on each part, and even if only one pin fails the part is considered to have failed
the test. Therefore, we expect our model’s predicted withstand levels to be higher than the
qualification withstand voltage because there will likely be a spread in the sample data. It
may be possible, through error analysis, to predict the deviation in performance of an IC
protection transistor based on the measured deviations of the test-structure design space.
In any case, it is necessary to account for the difference between the average withstand
voltage predicted by the model and the minimum withstand voltage determined through
product qualification.
5.1.4 Identification of Critical Current Paths
Predicting the ESD failure level of an IC presumes knowledge of the discharge current
path, so it is important to identify all potential paths between any pair of stressed pins. Fig.
5.59 shows the critical pull-up, pull-down, and supply-clamp circuits in an IC with
internal, external, and clock power supplies. For input-only pads, ESD protection is
provided by adding a “dummy” CMOS output buffer on the pad to form the pull-up and
pull-down circuits, with the gate of each circuit soft-tied to its respective source. For
output-only or bi-directional I/O pads, the large output driver doubles as the ESD
protection circuitry, with extra “dummy” poly fingers added in parallel if necessary.
In some cases of ESD stress, such as negative voltage on an I/O or VCC pad with respect
to VSS or positive voltage on an I/O pad with respect to VCC , the current path is just a
forward diode drop across the large drain-substrate junction of a protection circuit. For the
opposite stress polarities, however, the current path contains transistors operating in
snapback mode and/or diodes in reverse-breakdown mode. Since HBM (or CDM)
stressing of both polarities is performed on a given test and forward-biased diodes are
found to be very robust in our technology, the focus of the modeling is on bipolar
snapback.