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characterization, modeling, and design of esd protection circuits

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172 Chapter 6. Conclusion<br />

the internal VSS supply while the source is tied to the external VSS supply in order to<br />

reduce substrate noise. The isolation <strong>of</strong> the source from the substrate results in different<br />

ESD behavior since the discharge current path is altered. In the latter case, a cascoded gate<br />

(also called a stacked gate or split gate) pull-down transistor is used at the I/Os because the<br />

circuit, although <strong>design</strong>ed to operate using a 3.3V supply, must be able to tolerate a 5V<br />

signal on the I/Os in order to meet older circuit-board specifications (a st<strong>and</strong>ard pull-down<br />

transistor cannot be used in this case because 5V could develop across the transistor gate,<br />

which is only <strong>design</strong>ed to withst<strong>and</strong> a 3.3V signal). Stacking two gates in series affects the<br />

ESD response because the snapback voltage <strong>and</strong> snapback resistance are effectively<br />

doubled.<br />

In addition to applying the <strong>design</strong> methodology to different types <strong>of</strong> <strong>protection</strong> <strong>circuits</strong>,<br />

determining the feasibility <strong>of</strong> <strong>modeling</strong> CDM withst<strong>and</strong> voltages is also important because<br />

CDM is now the dominant ESD concern in the IC industry. Since CDM stress usually<br />

leads to dielectric damage <strong>of</strong> gate oxides, a different type <strong>of</strong> test structure may be required.<br />

For example, by connecting the input <strong>of</strong> an inverter circuit to the drain <strong>of</strong> an NMOS pulldown<br />

<strong>protection</strong> transistor we can determine how effectively the transistor would protect<br />

the input gates <strong>of</strong> an actual integrated circuit during CDM stress. Test structures might<br />

also be bonded into different types <strong>of</strong> packages to model the dependence <strong>of</strong> CDM<br />

robustness on the inductance <strong>and</strong> resistance <strong>of</strong> package leads.<br />

An important aspect <strong>of</strong> the methodology presented in this thesis is that a simple, empirical<br />

approach is taken to model ESD <strong>protection</strong> <strong>circuits</strong>. However, in the future we would like<br />

to integrate two-dimensional electrothermal device simulation <strong>and</strong> circuit simulation into<br />

the process to confirm the trends predicted by the empirical models. In doing so we may<br />

find that a more complex model is needed, i.e., something beyond second-order linear<br />

equations, in which case a more advanced <strong>modeling</strong> s<strong>of</strong>tware package would be required.

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