characterization, modeling, and design of esd protection circuits

5.3. Analysis 159
assumed to be isolated from each other. The final VHBM,ws value is still determined by
multiplying by the total width of the five fingers.)
As a result of the different number of fingers used in the model, Table 5.2 shows that the
predicted normalized withstand level is different for the full-I/O and input-only circuits
even though they have the same finger width and contact-to-gate spacing. Using the
proper parameters, the difference between modeled and experimental VHBM,ws values is
less than 5% for I/O vs. VSS testing. Note that the model predicts accurate values for the
10-finger device even though this requires extrapolation beyond the design-space limit of
six fingers.
A negative-voltage stress on an I/O with respect to VCC will turn on a supply-clamp
circuit in the same manner as a positive-voltage stress to VCC with respect to VSS because
in the former case the I/O is connected to VSS through the forward-biased drain-substrate
diode of the pull-down circuit. However, in Table 5.2 we see that while the withstand
voltage of the I/O vs. VCC stress for each lot is within reasonable range of the predicted
value, VHBM,ws for the VCC vs. VSS stressing is above the testing limit of 10,000V. Since
there are multiple supply clamps laid out at various points along the pad ring of the SRAM
circuit, it appears that during VCC vs. VSS stress two or more clamps turn on and act in
parallel to dissipate the ESD current. Based on model calculations for the snapback
voltage (6.8V for Lot 1, 7.0V for Lot 2) and snapback resistance (1.1Ω, 0.73Ω) of one
clamp circuit with all fingers conducting, the second-breakdown voltage (Vt2 , see Fig.
5.54 and Eq. (5.48)) is 10.8V for Lot 1 and 10.5V for Lot 2. These values are very close to
the expected trigger voltage of the clamp circuit, and thus it is reasonable to expect a
second clamp to turn on before the first clamp fails.
Turning to the I/O vs. VCC results in Table 5.2, consider that while the experimental
VHBM,ws is very close to the model prediction for Lot 1, it is much lower than predicted
for Lot 2 and is indeed lower than the Lot 1 experimental value even though the modeling
predicts higher performance for Lot 2. This result should make us suspicious of whether
the clamp circuit is operating as predicted in Lot 2 SRAMs. Although the snapback
voltage for the clamp circuit predicted by the model is about 6.9V for both lots, a lower
source/drain diffusion resistance in Lot 2 leads to a lower snapback resistance, with the
model predicting 5.5Ω per finger for Lot 1 and 3.7Ω per finger for Lot 2. Thus, one
possible explanation for the unexpectedly low experimental value of VHBM,ws in Lot 2 is