characterization, modeling, and design of esd protection circuits

2.2. Transmission Line Pulsing 29
ESD event unless the rise time of the pulse is much longer than that of the TLP pulse.
Experimentally the difference in Vt1 between dc sweeps and TLP pulses with 3ns rise
times is only one or two volts, so TLP-measured Vt1 values are still indicative of the
maximum input voltage created by pulses with much longer rise times.
2.2.2 Failure Power vs. Time to Failure
The short-duration pulses used to generate an I-V curve with TLP should be representative
of actual ESD events. For example, a 100ns square-wave pulse provides a stress similar to
a human-body model pulse, which has a decay time of approximately 150ns. A similar I-V
curve can be generated with a well-controlled quasi-steady state current sweep, but the
second-breakdown point will occur at a lower current due to the longer time spent at each
stress level (there is also a dependence of Vt1 , It1 , and other parameters on the height and
rise time of the input pulse). This is more representative of EOS damage. Intuitively, one
expects a device to fail at a lower pulse height if the pulse duration is longer. To quantify
this idea, a 3D thermal model has been proposed which defines four distinct regions of
power-to-failure vs. time-to failure [23,38,39]. This model assumes a rectangular-box
region of device heating in the drain-side junction depletion region of a MOSFET with a
spatially uniform, time-invariant power source ( Watts/cm 3 H = J ⋅ E
); constanttemperature
boundary conditions on all sides of the box (an infinite heat sink); and no
heating outside the box. As shown in Fig. 2.11, the length of the box, a, is equal to the
poly gate
gate oxide
c
b
a
p sub
Fig. 2.11 3D thermal box region (dotted lines) of heat dissipation in an
NMOS transistor subjected to a positive ESD pulse. The
dimension a is equal to the device width, b is related to the gate
length, and c is approximately equal to the diffusion depth.
n +
n LDD