12.12.2012 Views

characterization, modeling, and design of esd protection circuits

characterization, modeling, and design of esd protection circuits

characterization, modeling, and design of esd protection circuits

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

38 Chapter 2. ESD Circuit Characterization <strong>and</strong> Design Issues<br />

impedance outputs are connected to the drains <strong>of</strong> output-buffer transistors. Design <strong>of</strong><br />

output <strong>protection</strong> is thus more restricted than that <strong>of</strong> input <strong>protection</strong> because <strong>of</strong> low<br />

output-impedance requirements. For example, a well resistor may be placed between an<br />

input pad <strong>and</strong> the <strong>protection</strong> MOSFET to reduce the rise time <strong>of</strong> an ESD pulse, but such a<br />

resistor cannot be placed on an output pad because the increased impedance would exceed<br />

circuit specifications. Also, since the output-<strong>protection</strong> transistors <strong>of</strong>ten double as the<br />

CMOS output buffer, they must meet certain chip-performance specifications. As a result,<br />

output <strong>protection</strong> relies more on the proper layout <strong>of</strong> one or two transistors than on the use<br />

<strong>of</strong> creative circuit <strong>design</strong>s.<br />

Fig. 2.15a shows a simple diode <strong>protection</strong> scheme. The diodes are formed by source/<br />

drain diffusions in the p-substrate or n-well. When the circuit is powered up, diode D1 will<br />

become forward biased <strong>and</strong> conduct current for any input voltage greater than VCC + Vd ,<br />

where Vd is the forward diode drop. Similarly, diode D2 clamps any negative voltage<br />

below VSS - Vd . If the chip is not powered up <strong>and</strong> an ESD pulse is incident between the<br />

input <strong>and</strong>, say, VSS , the voltage will be clamped at either the breakdown voltage <strong>of</strong> the<br />

diode for a positive pulse (note we are neglecting the voltage drop across the dynamic<br />

resistance <strong>of</strong> the diode) or at -Vd for a negative pulse. The diodes should introduce<br />

minimal leakage current <strong>and</strong> a negligible parasitic capacitance to the circuit since they are<br />

normally reverse biased. Series resistors can be used in conjunction with diodes (or other<br />

devices) in input <strong>protection</strong> <strong>circuits</strong>, as shown in Fig. 2.15b, to create a potential drop from<br />

the pad to the diode <strong>and</strong> thus reduce the voltage at the input gates. Using a diffused resistor<br />

distributes the resistance <strong>and</strong> introduces an additional distributed diode, resulting in a<br />

lower gate voltage than that created by a simple polysilicon resistor. Addition <strong>of</strong> a series<br />

resistor aids circuit <strong>protection</strong> by slowing down transients (e.g., a machine-model<br />

waveform would be transformed into a HBM-like waveform), but by the same token it can<br />

reduce circuit speed performance by increasing RC time constants.<br />

Although diode <strong>circuits</strong> are simple to implement <strong>and</strong> may have provided sufficient ESD<br />

<strong>protection</strong> in the past, there are a few reasons why they are no longer adequate for protecting<br />

today’s smaller technologies. First, the dynamic resistance <strong>of</strong> a reverse-biased diode<br />

may be too high to keep voltages clamped at a safe level unless the diode area is very<br />

large. For example, a 250 µm2 area <strong>of</strong> diode with a typical impedance <strong>of</strong> 5000 Ω-µm2 has<br />

a resistance <strong>of</strong> 20Ω <strong>and</strong> will sustain 20V at a stress current <strong>of</strong> 1A, a voltage well above the<br />

dielectric threshold <strong>of</strong> a thin gate oxide. The potential drop can <strong>of</strong> course be reduced by

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!