characterization, modeling, and design of esd protection circuits

90 Chapter 3. Simulation: Methods and Applications
fixed charges because each has a unique effect on the transconductance and substratecurrent
characteristics.
Based on the findings of a relation between ESD stress and latent dielectric damage due to
charge injection, it should be beneficial to study dielectric damage in ESD simulations.
Since models for hot-carrier injection, fixed charge and charge traps at an oxide interface,
and fixed charge within an oxide region are implemented in some 2D device simulators
[29,30,44], it may be possible to simulate the dielectric damage incurred by a device
during an ESD event, although a model of charge trapping within the oxide would also be
required. Instead of modeling the change in the amount of trapped oxide charge during a
transient ESD simulation, it would be easier and perhaps just as informative to simply
look at the calculated hot-carrier gate current for each solution. In TMA-MEDICI, gate
current analysis is available as a post-processing tool. That is, gate current is calculated
based upon the electric field and current density profiles of a solution, but the resultant
value is not fed back into the solver to create a self-consistent solution in which all current
sources and sinks sum to zero. Usually this is not a problem because the gate current is
several orders of magnitude lower than the source and drain current. The gate-current
calculation is based on the lucky-electron model [53], which determines the number of
carriers injected into the gate from a product of probabilities that are a function of the local
electric field and scattering mean free paths. Since the use of gate-current simulation is
only being investigated qualitatively in this section, a detailed discussion of the luckyelectron
model is deferred to the TMA-MEDICI manual [29] and default model
coefficients will be assumed.
In Fig. 3.36, the gate current is plotted vs. time for two simulated 50/0.75µm MOSFETs
subjected to a square-wave pulse with a 3ns rise time, as depicted in the inset of Fig. 3.34.
In one structure the gate is grounded, while in the other a 10KΩ bounce resistor, described
in Section 2.3, has been placed between the gate electrode and ground to facilitate turn-on
of the transistor (normal current through this resistor is not included in the gate-current
plot). For both devices, the gate current increases as the electric field and avalanche
breakdown build up in the drain-substrate junction and reaches a peak at the time the
device enters snapback. In the case of the grounded-gate device, zero potential on the gate
favors injection of holes into the oxide. Once this device turns on and the drain voltage
drops, the electric field drops and less energy is available for the holes to surmount the
oxide barrier, so the gate current falls off. In the case of the device with the gate-bounce