characterization, modeling, and design of esd protection circuits

154 Chapter 5. Design and Optimization of ESD Protection Transistor Layout
circuit. This would lead to an unpredictable, low-voltage failure to which our modeling
cannot be applied.
5.2 Application
NMOS ESD test structures were laid out and characterized using TLP and HBM testing
for an AMD 0.35µm CMOS process. The design space covers finger widths between 25
and 150µm, DGS between 4.4 and 7.4µm, and SGS between 2.2 and 4.2µm for singlefinger
structures and multiple-finger structures with two to six fingers. In order to keep the
number of test structures in the design space relatively small, gate length was not used as a
factor in this study. The total design space, comprised of 18 structures, is not optimal
because layout was not performed with empirical modeling in mind. Catalyst requires 20
structures in order to calculate model coefficients for all linear, quadratic, and interaction
terms for four factors. However, since not all possible model terms are needed to describe
the responses, our design space is adequate. The responses for which model equations are
derived are Vsb , Rsb , IHBM,ws , and VHBM,ws . The trigger voltage, Vt1 , is not modeled
because it is mainly dependent on gate length and gate-bounce resistance, parameters
which are not varied.
Model terms for each response are chosen based on physical reasoning and observed
single-factor dependencies. Examining the snapback voltage first, note that since Vsb is
the voltage required to sustain parasitic bipolar operation, it should be the sum of the
BVCEO of the intrinsic device and the ohmic drops in the source and drain diffusions. The
intrinsic device size is a constant in the design space since gate length is not varied, and
therefore
V sb
= + a1( DGS)
+ a2 ( SGS)
. (5.51)
a 0
The snapback resistance should always be proportional to the total device width, assuming
all fingers are conducting. Thus, the Rsb response is normalized by the total width and Eq.
(5.50) is rewritten as
R sb
⋅ ( Wn)
= b0 + b1( DGS)
+
b2 ( SGS)
. (5.52)