characterization, modeling, and design of esd protection circuits

86 Chapter 3. Simulation: Methods and Applications
3.7 Simulation of Dielectric Failure and Latent ESD Damage
The previous two sections have addressed simulation of the MOSFET snapback I-V
curve, second breakdown, and thermally induced failure. As discussed in Section 1.1,
dielectric breakdown and latent damage are also important failure mechanisms in ESD
protection circuits. Although the applicability of numerical device simulation to these
types of failures is not as apparent as it is for thermal failure, the ability to monitor the
electric field in the oxide region and the lattice-temperature profile in the silicon and to
calculate hot-carrier injection current affords at least a qualitative examination of
dielectric and latent damage. Dielectric breakdown is a threat both in the gate oxides of
the input circuit being protected and in the thin-gate protection-circuit transistors which
absorb an ESD pulse. Damage of the input gate oxide will most likely occur if the input
(gate) voltage is not properly clamped by the protection device during an ESD stress (refer
to Fig. 2.16), leading to time-dependent dielectric breakdown (TDDB) [64]. In the
protection transistor, oxide damage is more likely due to hot-carrier injection resulting
from the high ESD current than from pure high-voltage stress. Oxide damage due to highvoltage
stress may occur, but since the protection-transistor oxide area is typically larger
than the input-circuit oxide area, and since the input voltage is partially dropped across the
n + drain diffusion of the protection transistor, the input-circuit oxide is much more likely
to fail before the protection-circuit oxide. Nonetheless, it is simplest to study all dielectric
failure mechanisms in the same device, so simulations will focus on the protection device
while acknowledging that a high-voltage stress on the oxide implies an even higher stress
on the input gate being protected. As discussed in Chapters 1 and 2, latent damage, lowlevel
damage which does not cause immediate circuit failure but rather reduces the
circuit’s operational lifetime, has been attributed to oxide damage as well as to localized
silicon melting in MOSFETs. Thus, some of the simulation techniques which apply to
dielectric breakdown should also apply to latent failures.
Device simulators model the transport of charge carriers, but there is no way to model the
movement or melting of the silicon lattice because the grid defining the structure is fixed
and there is no mechanism for modeling the solid-liquid phase change. Instead, it must be
assumed that when the modeled temperature exceeds 1688K over some area of a device,
melting will occur (TMA-MEDICI allows the lattice temperature to reach 2000K,
although the meaningfulness of a temperature greater than the silicon melting point is
questionable). For dielectric failure, damage will be inferred from two phenomena: