characterization, modeling, and design of esd protection circuits

4.1. Calibration Procedure 115
perimeter). As shown in Fig. 4.43, reducing the temperature dependence of the II
coefficients has the same effect as reducing the peak temperature in the device, which is
not surprising since reducing the temperature has the same effect on the mean free path as
increasing Ep . A similar result was obtained for a simulation in which the hightemperature
degradation of the bulk mobility was eliminated: the I-V roll-off was reduced
or delayed, but it was not eliminated. It can be concluded from these simulations that the
mobility and II models could not be modeled so inaccurately as to be solely responsible
for the severe roll-off of the I-V snapback curve.
Since the unreasonable roll-over is not explained by any of the theories above, it is most
likely due to improper modeling of the electric-field profile in the region of highest II
generation, i.e., under the gate in the drain LDD. The layout of the simulation grid
partially determines the field profile and thus the II generation, as was already pointed out
at the beginning of this subsection when the dependence of the breakdown voltage on the
simulation grid was discussed. In simulations run for a MOSFET with no LDD region, the
roll-over, although definitely still present, is significantly reduced. One possible reason
that an LDD device would be harder to simulate is that the electric-field profile is more
complicated in the region of high current density. When the device current is less than
about 100µA/µm, the II modeling appears to be correct, but for higher current in the
snapback regime the grid problems are disclosed. The problem of grid definition definitely
needs more attention, but since modifying the grid layout would require another iteration
of calibrating the II coefficients and possibly the mobility coefficients, a solution to the
problem was not pursued. As it turns out, the snapback resistance can still be extracted
from the simulated I-V curve by measuring the tangent just after snapback, where the peak
temperature is not much above 297K. As shown by the curves of Fig. 4.43, the slope is
approximately constant for the first 0.5mA/µm above the current corresponding to
minimum device voltage. Values for the simulated Rsb vs. CGS will be given in the
section on snapback I-V results and compared to the experimental values.
The final parameter to be considered in the dc snapback simulations is the trigger voltage,
Vt1 . In the TLP experiments, a trend could not be seen between variation in the contact-togate
spacing and Vt1 . Values ranged from 11.7V to 12.0V (BVDSS is about 11.2V), but the
lowest and highest Vt1 did not correspond to the lowest and highest CGS. The lack of a
trend is not surprising. Since the device current before snapback is less than 5mA and the
difference in series source/drain resistance between 3µm CGS and 8µm CGS is about 12Ω