12.12.2012 Views

characterization, modeling, and design of esd protection circuits

characterization, modeling, and design of esd protection circuits

characterization, modeling, and design of esd protection circuits

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

136 Chapter 4. Simulation: Calibration <strong>and</strong> Results<br />

will be approximately the same regardless <strong>of</strong> the number <strong>of</strong> fingers chosen, so we will<br />

choose to build the device with five parallel poly fingers, each 50µm long. Since the total<br />

width from the drain contacts to the source contacts <strong>of</strong> a finger is approximately two times<br />

CGS, the total area will be about 50µm X 50µm. With five poly fingers, there will be three<br />

fingers coming <strong>of</strong>f <strong>of</strong> the input pad into the <strong>protection</strong> device (refer to Fig. 2.19).<br />

Since the measured <strong>and</strong> simulated grounded-gate trigger voltage <strong>of</strong> the <strong>protection</strong><br />

structures is very close to 12V, a gate-bounce resistor should be employed to provide a<br />

margin <strong>of</strong> safety against dielectric failure <strong>of</strong> the input gates. The simulated results <strong>of</strong> Vt1 vs. gate resistance in Fig. 4.48 show that a lumped gate resistance <strong>of</strong> 50kΩ between the<br />

gate electrode <strong>and</strong> the grounded source will reduce the trigger voltage by 1.2V for a<br />

50µm-wide device subjected to a pulse rise time <strong>of</strong> 16V/ns. Since the device being<br />

<strong>design</strong>ed has five fingers which are each 50µm wide <strong>and</strong> the drain-gate overlap<br />

capacitances add in parallel, a proportionately smaller gate resistance, i.e., 10kΩ, can be<br />

used to achieve the same amount <strong>of</strong> gate bounce. This resistance can most easily be<br />

created by placing a well resistor or tie-<strong>of</strong>f transistor with a resistance <strong>of</strong> 10kΩ between<br />

the common gate <strong>and</strong> the source or substrate pad. The gate bounce should not be made too<br />

great because if the gate potential remains significantly high after a finger snaps back, the<br />

high current in the finger will be concentrated at the surface <strong>and</strong> cause severe heating at a<br />

much lower current level than if the current is distributed evenly along the vertical<br />

junction pr<strong>of</strong>ile. The reduction in Vt1 <strong>of</strong> 1.2V created by the 10kΩ resistor, which makes<br />

the value <strong>of</strong> Vt1 10.6V, is probably a reasonable value.<br />

Assuming the fingers turn on one at a time, which is the worst-case scenario but is also the<br />

most probable scenario considering the r<strong>and</strong>om finger-to-finger variations in layout <strong>and</strong><br />

the very brief (~1ns) turn-on time, after the first finger turns on the input (drain) device<br />

voltage, Vdev , will rise with device current, Idev , as (refer to Fig. 4.41)<br />

Vdev = Vsb + Rsb ⋅ Idev, (4.40)<br />

where Rsb is the snapback resistance <strong>of</strong> one finger. For the device to work properly, a<br />

second finger must turn on (snap back) before Idev reaches the failure level for one finger,<br />

641mA. In terms <strong>of</strong> the device parameters,<br />

Idev =<br />

( Vt1 – Vsb) ⁄ Rsb < 641mA . (4.41)

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!