characterization, modeling, and design of esd protection circuits

4 Chapter 1. Introduction
device failure, i.e., shorts and opens, or the more subtle damage of increased leakage.
Second breakdown is a positive-feedback process and is a well-known phenomena in
power devices. A physical explanation of second breakdown is given in Chapter 2.
Dielectric failure and thermal failure are generally considered to be catastrophic, i.e., the
IC is no longer functional after the ESD stress. However, as has been noted above there is
another type of ESD damage referred to as latent damage, a phenomenon which is well
documented but is not well understood. Latent damage consists of increased leakage
current or reduced oxide integrity, without loss of functionality, of a stressed circuit
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. A latent ESD failure is defined as “a malfunction that occurs in use conditions
because of earlier exposure to ESD that did not result in an immediately detectable
discrepancy [16].” Latent damage is often bake-recoverable, i.e., reversible. Low-level
leakage (an increase in leakage which remains below the failure threshold), also referred
to as soft failure, may be due to injection of hot carriers into the gate oxide, which would
cause a threshold-voltage shift, or to damage in the silicon resulting from localized
melting, or to both. A small damage site could act like a high-resistance filament across a
diode junction, thereby increasing the leakage current to a significant but non-catastrophic
level. It is certainly possible for second breakdown to occur, and even for melting to occur,
without catastrophic failure if there is not enough energy in an ESD pulse to cause
widespread damage. Polgreen et al. [8] found this to be true for MOSFETs with widths
below a certain critical value. They postulated that a certain amount of total current is
needed to cause widespread device damage. In narrow devices, when a hot spot forms all
of the available current rushes to the spot, but there is not enough total current to cause
catastrophic damage. Extensive damage will not occur until the device is driven deeper
into second breakdown by being stressed with a higher current.
1.2 Characterizing ESD in Integrated Circuits
In order to characterize the susceptibility of an IC to ESD damage, the IC must be tested
using models which accurately simulate real ESD events. These models should be
standardized so that testing is consistent and reliability can be defined quantitativelyattributes
which make a figure of merit and design goals possible. Actual ESD stresses
occur during wafer fabrication, packaging, testing, or any other time the circuit comes in
contact with a person or machine. The majority of stresses occur between two pins of an
IC package when the chip is not powered up, a fact reflected in the setup of ESD