characterization, modeling, and design of esd protection circuits

3.6. Extraction of MOSFET Pf vs. tf Curve 77
I device / mA
50
40
30
20
10
0
V, I
V 2 , I 2
-10
0 2 4 6 8 10
Vdevice / volts
Fig. 3.30 I-V curves of a single TLP simulation (solid line, V in =50V in the
circuit of Fig. 3.27) and of points resulting from a group of TLP
simulations (dashed line). Point (V 1 , I 1 ) corresponds to the turn-on of
the parasitic bipolar transistor. V 2 and I 2 are the device voltage and
current values at the time the input pulse reaches its peak; in this case
t rise = 1ns. The quasi-steady state of the pulse is the point (V, I).
In studying the I-V characteristics of a simulated ESD protection transistor in the next
chapter, the general strategy will be to run a dc curve trace to extract the snapback voltage,
Vsb , and snapback resistance, Rsb , and then run transient TLP simulations to extract the
trigger point and second breakdown/thermal failure point. Different sets of TLP
simulations must be run for each iteration of a gate-bouncing implementation in order to
see the effects on the trigger voltage and current. Simulation of the second-breakdown
portion of the I-V curve is very important in itself and is the subject of the next section.
3.6 Extraction of MOSFET P f vs. t f Curve
V 1 , I 1
Although inclusion of the thermal-diffusion equation in device simulation is useful for
studying phenomena such as high-temperature degradation of mobility and impact