characterization, modeling, and design of esd protection circuits

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46 Chapter 2. ESD Circuit Characterization and Design Issues parameters should not change, which means Rsb should decrease. However, if a gate resistor or other method is used to couple the gate bias to the input, a larger W implies a larger drain-gate overlap capacitance and thus an increase in coupling (see Eq. (2.14)) and a reduction in Vt1 due to more MOS transistor action. Another point to make is that as discussed in Section 1.1, for very small device widths the failure current appears to be independent of W because some overall current is needed to create severe damage. This is not a contradiction of the It2 ∝ W rule because in such cases failure does not follow immediately after second breakdown, so there is a difference between the failure current and It2 . Note that if device operation is not uniform but rather the current and voltage or electric field are concentrated at a corner or edge, second breakdown will occur sooner than predicted, i.e., It2 will not scale linearly with width. • Source/Drain (S/D) junction depth and profile -- Deeper junctions have a larger area over which current is distributed and thus a lower current density for a given current level. In other words, the depth of the box in the 3D thermal model is larger, which Table 2.1 Dependence of critical I-V parameters on process and layout. An up or down arrow signifies that the I-V parameter increases or decreases, respectively, as the process or layout parameter increases or as otherwise noted. Double arrows indicate a primary dependence, while a single arrow represents a second-order or side effect. ND signifies that there is little or no dependence on the parameter. Parameter Vbd Vt1 It1 Vsb Rsb Vt2 It2 Gate length ND ↑↑ ↑ ↑↑ ↑ ↑ ↑↑ Gate width ND ↓a ↑↑ ND ↓ ND ↑↑ S/D junction depth (1 / curvature) ↓↓ ↓ ND ↓ ↓ ↑ ↑↑ Contact-gate spacing ↑ ↑ ND ↑↑ ↑↑ ↑ ND Remove silicide ND ↑ ND ↑↑ ↑↑ ↑ ↑↑ Gate bias/bounce ↓↓ ↓↓ ↓↓ ND ND ND ND Block LDD implant ↑↑ ↑ ND ↑ ↑ ↑ ↑↑b Substrate resistance ↓ ↓ ↓↓ ND ND ND ↓ a. If gate coupling is used. b. If LDD junction is shallow compared to S/D junction.
2.4. Dependence of Critical MOSFET I-V Parameters on Process and Layout 47 increases It2 . The breakdown voltage, Vbd , of a junction increases as the curvature increases, but this effect is much less pronounced in graded junctions than in abrupt junctions [42]. A deeper junction also has a lower resistivity and will significantly decrease Rsb if the spacing between the gate and the source/drain contacts is large (see below). This decreased S/D resistance reduces Vsb and, to a lesser degree, Vt1 . It1 is independent of small variations in junction depth because the junction depth does not affect the level of impact-ionization generation needed to induce snapback. • Contact-to-gate spacing -- Increasing the spacing between the gate and the drain contacts increases the series resistance between the input and intrinsic circuit. The main effect of increasing the spacing is an increase in the snapback resistance and snapback voltage. If It2 is not affected, a larger Rsb implies a larger Vt2 (It2 may be affected for longer stress times in which dissipation of heat is important over a wider area extending into the drain diffusion region). There will also be an increase in Vbd and Vt1 , although the current level just before snapback is usually about a milliamp and thus the added potential drop in the drain diffusion may be inconsequential. Increasing the spacing from the gate to the source contacts will have the same effects since it is also just an introduction of more series resistance in the circuit. • Silicide -- Varying the contact-to-gate spacing will only have a significant effect if the diffusions are not silicided. In current MOS technologies a titanium or tungsten silicide is placed over the S/D diffusions to reduce series resistance and thus enhance circuit performance. A typical n + S⁄ D diffusion resistance is on the order of 4 Ω/❏, whereas a non-silicided diffusion has a resistivity of about 60 Ω/❏. Silicided diffusions are a disadvantage in ESD circuits because they concentrate current at the surface, which reduces It2 by increasing current density, and because they eliminate the ballast resistance (Rsb ) between the input and the intrinsic device needed to ensure uniform turn-on in a multifingered structure (see next section). Again, note that a reduction in series resistance implies a reduction in Vsb and a slight reduction in Vt1 . In some technologies a “resist mask” is used to block silicidation of S/D diffusions, and this mask is normally used for ESD protection circuits. • Gate bias -- As discussed in the previous section, biasing the gate by coupling the gate voltage to the input reduces Vt1 by aiding the onset of snapback through increased drain current; the snapback and second-breakdown regions are unaffected. Maximum reduction in the trigger voltage is attained by biasing the gate just above the threshold
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CHARACTERIZATION, MODELING, AND DES
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Abstract For more than 20 years, su
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Acknowledgments This work could not
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Contents Abstract iii Acknowledgmen
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6 Conclusion 165 6.1 Contributions
Page 11 and 12: List of Figures 1.1 ESD protection
Page 13 and 14: 3.32 Simulated 1/∆T vs. time and
Page 15 and 16: A.65 The output file, bvceo.out, fo
Page 17 and 18: Chapter 1 Introduction Electrostati
Page 19 and 20: 1.1. ESD in the Integrated Circuit
Page 21 and 22: 1.2. Characterizing ESD in Integrat
Page 23 and 24: 1.3. Protecting Integrated Circuits
Page 25 and 26: 1.4. Numerical Simulation 9 simulat
Page 27 and 28: 1.5. Design Methodology 11 process.
Page 29 and 30: 1.6. Outline and Contributions 13 A
Page 31 and 32: Chapter 2 ESD Circuit Characterizat
Page 33 and 34: 2.1. Classical ESD Characterization
Page 35 and 36: 2.2. Transmission Line Pulsing 19 i
Page 37 and 38: 2.2. Transmission Line Pulsing 21 (
Page 39 and 40: 2.2. Transmission Line Pulsing 23 (
Page 41 and 42: 2.2. Transmission Line Pulsing 25 I
Page 43 and 44: 2.2. Transmission Line Pulsing 27 I
Page 45 and 46: 2.2. Transmission Line Pulsing 29 E
Page 47 and 48: 2.2. Transmission Line Pulsing 31 w
Page 49 and 50: 2.2. Transmission Line Pulsing 33 a
Page 51 and 52: 2.2. Transmission Line Pulsing 35 F
Page 53 and 54: 2.3. Overview of Protection Circuit
Page 61: 2.4. Dependence of Critical MOSFET
Page 65 and 66: 2.5. Design Methodology 49 the subs
Page 67 and 68: 2.5. Design Methodology 51 The perf
Page 69 and 70: 2.5. Design Methodology 53 enter se
Page 71 and 72: Chapter 3 Simulation: Methods and A
Page 73 and 74: 3.1. Lattice Temperature and Temper
Page 81 and 82: 3.2. Curve Tracing 65 line (c) in F
Page 83 and 84: 3.3. Mixed Mode Simulation 67 x n-1
Page 85 and 86: 3.3. Mixed Mode Simulation 69 V c C
Page 87 and 88: 3.4. Previous ESD Applications 71 v
Page 89 and 90: 3.4. Previous ESD Applications 73 I
Page 91 and 92: 3.5. Extraction of MOSFET I-V Param
Page 93 and 94: 3.6. Extraction of MOSFET Pf vs. tf
Page 103 and 104: 3.7. Simulation of Dielectric Failu
Page 111 and 112: Chapter 4 Simulation: Calibration a
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4.1. Calibration Procedure 97 and t
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4.1. Calibration Procedure 99 conta
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4.1. Calibration Procedure 101 4.40
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4.1. Calibration Procedure 103 Afte
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4.1. Calibration Procedure 105 past
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4.1. Calibration Procedure 107 whic
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4.1. Calibration Procedure 109 simu
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4.1. Calibration Procedure 111 (a)
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4.1. Calibration Procedure 113 wher
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4.1. Calibration Procedure 115 peri
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4.1. Calibration Procedure 117 simu
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4.1. Calibration Procedure 119 volt
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4.2. MOSFET Snapback I-V Results 12
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4.2. MOSFET Snapback I-V Results 12
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4.3. Device Failure Results 125 V t
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4.3. Device Failure Results 127 alr
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4.3. Device Failure Results 129 act
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4.3. Device Failure Results 131 (a)
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4.3. Device Failure Results 133 (a)
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4.4. Design Example 135 reached, th
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4.4. Design Example 137 Using value
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Chapter 5 Design and Optimization o
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5.1. Methodology 141 5.1 Methodolog
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5.1. Methodology 143 W L DGS SGS Co
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5.1. Methodology 145 reaches its pe
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5.1. Methodology 147 the same withs
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5.1. Methodology 149 various respon
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5.1. Methodology 151 needed to desc
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5.1. Methodology 153 The actual pat
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5.2. Application 155 To determine h
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5.3. Analysis 157 are flat, a direc
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5.3. Analysis 159 assumed to be iso
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5.4. Optimization 161 Qualitatively
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5.5. Summary of Design Methodology
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Chapter 6 Conclusion In the integra
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6.1. Contributions 167 TLP was show
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6.2. Future Work 169 most ESD quali
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6.2. Future Work 171 Significant wo
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Appendix A Tracer User’s Manual S
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A.3. CONTROL Card 175 A.3 CONTROL C
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A.4. FIXED Card 177 A.4 FIXED Card
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A.5. OPTION Card 179 • DAMP is a
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A.5. OPTION Card 181 A.5.4 Examples
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A.6. SOLVE Card 183 if the voltage
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A.7. Input Deck Specifications 185
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A.9. Examples 187 column contains c
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A.9. Examples 189 fixed num = 1 typ
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A.9. Examples 191 Collector Current
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A.9. Examples 193 title mes.pis mes
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A.9. Examples 195 simulator to use.
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A.9. Examples 197 #Soln #Vctrl Ictr
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Bibliography [1] T.J. Green and W.K
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Bibliography 201 [20] C. Duvvury, R
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Bibliography 203 [42] S.M. Sze, Phy
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Bibliography 205 [63] R. van Overst
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