characterization, modeling, and design of esd protection circuits

1.3. Protecting Integrated Circuits from ESD 7
hole trapping in the gate oxide as well as interface-state generation, leading to a shift in
the threshold voltage [25]. The hole trapping can increase the susceptibility to timedependent
dielectric breakdown (TDDB) of the gate oxide. (TDDB refers to the observed
phenomenon that the higher a stress voltage is, the less time it takes to damage the oxide
being stressed.) To avoid being damaged, protection circuits should minimize self-heating
by keeping current densities and electric fields in the silicon low and prevent dielectric
breakdown of the gate oxides in the protection circuit by minimizing the electric fields
across the oxides.
Although this thesis focuses on protection circuits between input/output (I/O) pins and
supply pins, ESD phenomena can occur across any pair of pins, e.g., I/O vs. I/O and VCC vs. VSS . Protection circuits are not placed between the I/O pins of a package, and even
though a protection diode or transistor is usually placed between the two supply pins,
there is no guarantee that an electrostatic discharge will go through this path because the
circuits in the chip may provide a lower-resistance path. ESD events between I/Os and
between supplies lead to “far-internal” damage, i.e., the discharge paths lead through the
actual working circuit, and thus damage can occur in any number of places [20]. Modeling
of this behavior and design of protection are difficult because the discharge path is not
known a priori and more circuit elements are involved.
A few examples of ESD protection circuits are shown in Fig. 1.1. If the circuit of Fig. 1.1a
is powered up, diode D1 will turn on and conduct current for any input voltage greater
than VCC + Vd , where Vd is the forward diode drop. Similarly, diode D2 will clamp any
negative voltage below VSS - Vd . If the chip is not powered up and an ESD pulse is
incident between the input and, say, VSS , the voltage will be clamped at either the reverse
breakdown voltage of the diode for a positive pulse or at -Vd for a negative pulse. The
PMOS (M1) and NMOS (M2) devices of Fig. 1.1b behave similarly, with the drainsubstrate
junctions taking the place of the diodes. One major difference is that the drainsubstrate
junction reverse breakdown triggers the MOS device into a snapback mode in
which the drain voltage drops due to the turn-on of the lateral parasitic bipolar transistor
formed by the drain, channel, and source regions. Note that the output buffer is self
protecting, i.e., the transistors of the output buffer serve as the protection circuit. Finally,
Fig. 1.1c is an example of a more complex input protection circuit consisting of two
NMOS devices and a well resistor. The merits of this circuit as well as a more complete
description of the functionality of all the circuits are presented in Chapter 2.