characterization, modeling, and design of esd protection circuits

122 Chapter 4. Simulation: Calibration and Results
CGS decreases, then the slope of the Rsb vs. CGS curve should be lower at low CGS,
implying that Rsb is really positive as CGS approaches zero, as it must be. To determine
what parameters do in fact play a role, experiments and simulations need to be run on
structures with lower contact-to-gate spacing. However, interpolating values of Rsb for
CGS between 3µm and 8µm should be a safe practice.
In 2D simulations, any resistance is inversely proportional to device width because the
simulations are effectively normalized in the width dimension. However, Fig. 4.46 shows
that for real structures the extracted snapback resistance is not proportional to the inverse
device width for widths greater than 50µm. Once again, this is a result of device heating
and the consequent increase in device resistance at high current levels. For a given current
density, heating is more severe in a wider structure because the center of the device is farther
away from the structure edges where heat can be dissipated. Therefore, the extracted
snapback resistance for wide devices is higher than predicted by the narrow-width line fit.
R sb / Ω
20
16
12
8
4
0 0.00 0.01 0.02 0.03 0.04
1 / (Gate Width / µm)
382 Ω-µm
0.05
Fig. 4.46 Experimental snapback resistance, Rsb , (connected points) vs. inverse gate
width, W, for 0.75µm test structures. The dashed line indicates that
Rsb × W = 382Ω-µm for gate widths less than 50µm.