characterization, modeling, and design of esd protection circuits

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178 Appendix A. Tracer User’s Manual A.5 OPTION Card A.5.1 Description An OPTION card is used to specify convergence criteria and solution-method options for any open electrodes, parameters which affect the smoothness and step-size control of the trace, which PISCES solution files are saved, and whether extra solution data is saved in outputfile. A.5.2 Syntax Simulations with one or two open contacts: [ABSMAX=] [RELMAX=] [DAMP=] [TRYCBC=] Smoothness and step-size control: [ANGLE1=] [ANGLE2= [ANGLE3=] [ITLIM=] [MINCUR=] [MINDL=] Control of output files: [FREQUENCY=] [TURNINGPOINTS=] [VERBOSE=] A.5.3 Parameters • ABSMAX is the maximum current allowed in an open contact and is only relevant when open contacts are used and voltage biases are applied to these contacts. Convergence is satisfied when either the ABSMAX or RELMAX condition is met. Default: 1.0X10 -19 A/µm. • RELMAX is the maximum ratio of open-contact current to control-electrode current and is only relevant when open contacts are used and voltage biases are applied to these contacts. Convergence is satisfied when either the ABSMAX or RELMAX condition is met. Default: 1.0X10-9 .
A.5. OPTION Card 179 • DAMP is a number between 0 and 1.0 determining how quickly Tracer will converge on an open-contact solution using voltage biasing. The closer DAMP is to 1.0, the more quickly Tracer will converge, but there is also an increased chance of slower convergence due to overshoot. Usually the user should not be concerned with the value of DAMP. Default: 0.9. • TRYCBC is used only if there is an open contact. Tracer will only attempt to use zero-current biasing when the current of the control electrode is greater than TRYCBC. Otherwise, voltage biasing is used. In most cases the user does not have to worry about this parameter. Default: 1.0X10-17A/µm. • ANGLE1, ANGLE2, and ANGLE3 are critical angles (in degrees) affecting the smoothness and step size of the trace. They are described in detail in [28]. If the difference in slopes of the last two solution points is less than ANGLE1, the step size will be increased for the next projected solution. If the difference is between ANGLE1 and ANGLE2, the step size remains the same. If the difference is greater than ANGLE2, the step size is reduced. ANGLE3 is the maximum difference allowed, unless overridden by the MINDL parameter. ANGLE2 should always be greater than ANGLE1 and less than ANGLE3. Defaults: ANGLE1 = 5 o , ANGLE2 = 10 o , ANGLE3 = 15 o . • ITLIM is the maximum number of Newton loops for a given solution as specified in the method card of the PISCES input deck. The user should make sure that the value of ITLIM specified here is the same as that in the input deck. In certain cases, a PISCES solution may be aborted in Tracer because the solution will not converge within the given number of iterations. In some of these cases Tracer will try to redo the solution with a doubled number of iterations. If ITLIM is specified on the OPTION card, such attempts will be made. If there is no itlim statement or ITLIM=0, no attempts will be made. It is recommended that ITLIM be set to a low value, around 10 or 15 (or at least high enough to allow convergence of the initial solution). However, for GaAs devices a larger ITLIM of 20 or 25 is recommended. Default: 0. • MINCUR is the value of the control current, in A/µm, above which Tracer carefully controls step size and guarantees a smooth trace. Below this current level, the program simply takes voltage steps as large as possible, i.e., as long as numerical convergence can be achieved, without regard for smoothness. If MINCUR is set to 0.0, Tracer will not begin smoothness control until it is past the first sharp turn in the I-V curve. This value should be used when the user is only interested in the rough location of a break in
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CHARACTERIZATION, MODELING, AND DES
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Abstract For more than 20 years, su
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Acknowledgments This work could not
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Contents Abstract iii Acknowledgmen
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6 Conclusion 165 6.1 Contributions
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List of Figures 1.1 ESD protection
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3.32 Simulated 1/∆T vs. time and
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A.65 The output file, bvceo.out, fo
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Chapter 1 Introduction Electrostati
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1.1. ESD in the Integrated Circuit
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1.2. Characterizing ESD in Integrat
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1.3. Protecting Integrated Circuits
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1.4. Numerical Simulation 9 simulat
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1.5. Design Methodology 11 process.
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1.6. Outline and Contributions 13 A
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Chapter 2 ESD Circuit Characterizat
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2.1. Classical ESD Characterization
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2.2. Transmission Line Pulsing 19 i
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2.2. Transmission Line Pulsing 21 (
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2.2. Transmission Line Pulsing 23 (
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2.2. Transmission Line Pulsing 25 I
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2.2. Transmission Line Pulsing 27 I
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2.2. Transmission Line Pulsing 29 E
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2.2. Transmission Line Pulsing 31 w
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2.2. Transmission Line Pulsing 33 a
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2.2. Transmission Line Pulsing 35 F
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2.3. Overview of Protection Circuit
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2.4. Dependence of Critical MOSFET
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2.4. Dependence of Critical MOSFET
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2.5. Design Methodology 49 the subs
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2.5. Design Methodology 51 The perf
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2.5. Design Methodology 53 enter se
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Chapter 3 Simulation: Methods and A
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3.1. Lattice Temperature and Temper
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3.2. Curve Tracing 65 line (c) in F
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3.3. Mixed Mode Simulation 67 x n-1
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3.3. Mixed Mode Simulation 69 V c C
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3.4. Previous ESD Applications 71 v
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3.4. Previous ESD Applications 73 I
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3.5. Extraction of MOSFET I-V Param
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3.6. Extraction of MOSFET Pf vs. tf
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3.7. Simulation of Dielectric Failu
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Chapter 4 Simulation: Calibration a
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4.1. Calibration Procedure 97 and t
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4.1. Calibration Procedure 99 conta
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4.1. Calibration Procedure 101 4.40
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4.1. Calibration Procedure 103 Afte
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4.1. Calibration Procedure 105 past
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4.1. Calibration Procedure 107 whic
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4.1. Calibration Procedure 109 simu
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4.1. Calibration Procedure 111 (a)
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4.1. Calibration Procedure 113 wher
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4.1. Calibration Procedure 115 peri
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4.1. Calibration Procedure 117 simu
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4.1. Calibration Procedure 119 volt
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4.2. MOSFET Snapback I-V Results 12
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4.2. MOSFET Snapback I-V Results 12
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4.3. Device Failure Results 125 V t
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Page 145 and 146: 4.3. Device Failure Results 129 act
Page 147 and 148: 4.3. Device Failure Results 131 (a)
Page 149 and 150: 4.3. Device Failure Results 133 (a)
Page 151 and 152: 4.4. Design Example 135 reached, th
Page 153 and 154: 4.4. Design Example 137 Using value
Page 155 and 156: Chapter 5 Design and Optimization o
Page 157 and 158: 5.1. Methodology 141 5.1 Methodolog
Page 159 and 160: 5.1. Methodology 143 W L DGS SGS Co
Page 161 and 162: 5.1. Methodology 145 reaches its pe
Page 163 and 164: 5.1. Methodology 147 the same withs
Page 165 and 166: 5.1. Methodology 149 various respon
Page 167 and 168: 5.1. Methodology 151 needed to desc
Page 169 and 170: 5.1. Methodology 153 The actual pat
Page 171 and 172: 5.2. Application 155 To determine h
Page 173 and 174: 5.3. Analysis 157 are flat, a direc
Page 175 and 176: 5.3. Analysis 159 assumed to be iso
Page 177 and 178: 5.4. Optimization 161 Qualitatively
Page 179 and 180: 5.5. Summary of Design Methodology
Page 181 and 182: Chapter 6 Conclusion In the integra
Page 183 and 184: 6.1. Contributions 167 TLP was show
Page 185 and 186: 6.2. Future Work 169 most ESD quali
Page 187 and 188: 6.2. Future Work 171 Significant wo
Page 189 and 190: Appendix A Tracer User’s Manual S
Page 191 and 192: A.3. CONTROL Card 175 A.3 CONTROL C
Page 193: A.4. FIXED Card 177 A.4 FIXED Card
Page 197 and 198: A.5. OPTION Card 181 A.5.4 Examples
Page 199 and 200: A.6. SOLVE Card 183 if the voltage
Page 201 and 202: A.7. Input Deck Specifications 185
Page 203 and 204: A.9. Examples 187 column contains c
Page 205 and 206: A.9. Examples 189 fixed num = 1 typ
Page 207 and 208: A.9. Examples 191 Collector Current
Page 209 and 210: A.9. Examples 193 title mes.pis mes
Page 211 and 212: A.9. Examples 195 simulator to use.
Page 213 and 214: A.9. Examples 197 #Soln #Vctrl Ictr
Page 215 and 216: Bibliography [1] T.J. Green and W.K
Page 217 and 218: Bibliography 201 [20] C. Duvvury, R
Page 219 and 220: Bibliography 203 [42] S.M. Sze, Phy
Page 221 and 222: Bibliography 205 [63] R. van Overst
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