characterization, modeling, and design of esd protection circuits

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8 Chapter 1. Introduction D1 Fig. 1.1 ESD protection circuits in a CMOS technology: (a) diode protection; (b) CMOS transistor protection; (c) combination resistor/transistor protection circuit. 1.4 Numerical Simulation Input Output V CC (a) Bond pad D2 D2 Bond pad (b) V SS V CC Bond pad M2 M2 Bond pad (c) Bond pad V SS Numerical device simulation is an excellent tool for studying and designing transistors and diodes in IC technologies. Two-dimensional (2D) numerical device simulators such as PISCES-IIB [26,27] allow a user to create a 2D cross section of a semiconductor device, including definition of silicon and oxide regions, doping profiles, and electrodes, and then D1 Input Output M1 V CC M1 Rwell M2 V SS M1 Input
1.4. Numerical Simulation 9 simulate the I-V characteristics of the device. Coefficients for various mobility models, impact-ionization models, and material parameters can be adjusted to calibrate simulations to experimental data, but even uncalibrated simulations offer a qualitative understanding of device performance. Extensive analysis capabilities let the user examine the current density, electric field, impact-ionization generation rate, temperature, and many other properties at any location in the device for any simulated I-V point. If a calibrated simulation accurately models the physics of a device, it can be used to predict the dependence of device performance on process and layout variations. Ideally, simulations take the place of large numbers of process splits and layout structures, thereby reducing the time and cost of technology development. Simulation of ESD events is attractive because many ESD tests are destructive in nature and thus non-repeatable. In addition to predicting I-V curves, simulations can identify the point of device failure by monitoring the electric field, temperature, and other properties throughout the device during an ESD stress. The simulations can be either transient or steady state (dc). Transient simulations are used to model tests such as the human-body model, charged-device model, and transmission-line pulsing, while steady-state I-V sweeps are useful in predicting junction breakdown voltages and MOSFET snapback voltages. The ability to model ESD phenomena was greatly expanded by two recent advances in numerical device simulation. A curve-tracing technique [28] (also known as the continuation method) used to automate the steady-state simulation of complex I-V curves was implemented as a C-program wrapper around a device simulator. Automation of complex simulations such as latchup and snapback in MOSFETs saves the time and effort needed to manually change simulation boundary conditions any time there is a sharp turn in the I-V curve. A user manual for the curve tracer is included as an appendix. The other advance in device simulation is the incorporation of the thermal-diffusion equation [31] into the numerical equations to account for lattice temperature variation due to Joule heating and carrier generation and recombination. With this addition the device simulator solves the discreet thermal-diffusion equation in addition to the Poisson and carrier-continuity equations in either a coupled or decoupled manner. Thermal contacts and boundary conditions can be placed on the edges of the defined device, much as electrical contacts and boundary conditions are, to represent varying degrees of thermal
Page 1 and 2: CHARACTERIZATION, MODELING, AND DES
Page 3 and 4: Abstract For more than 20 years, su
Page 5 and 6: Acknowledgments This work could not
Page 7 and 8: Contents Abstract iii Acknowledgmen
Page 9 and 10: 6 Conclusion 165 6.1 Contributions
Page 11 and 12: List of Figures 1.1 ESD protection
Page 13 and 14: 3.32 Simulated 1/∆T vs. time and
Page 15 and 16: A.65 The output file, bvceo.out, fo
Page 17 and 18: Chapter 1 Introduction Electrostati
Page 19 and 20: 1.1. ESD in the Integrated Circuit
Page 21 and 22: 1.2. Characterizing ESD in Integrat
Page 23: 1.3. Protecting Integrated Circuits
Page 27 and 28: 1.5. Design Methodology 11 process.
Page 29 and 30: 1.6. Outline and Contributions 13 A
Page 31 and 32: Chapter 2 ESD Circuit Characterizat
Page 33 and 34: 2.1. Classical ESD Characterization
Page 35 and 36: 2.2. Transmission Line Pulsing 19 i
Page 37 and 38: 2.2. Transmission Line Pulsing 21 (
Page 39 and 40: 2.2. Transmission Line Pulsing 23 (
Page 41 and 42: 2.2. Transmission Line Pulsing 25 I
Page 43 and 44: 2.2. Transmission Line Pulsing 27 I
Page 45 and 46: 2.2. Transmission Line Pulsing 29 E
Page 47 and 48: 2.2. Transmission Line Pulsing 31 w
Page 49 and 50: 2.2. Transmission Line Pulsing 33 a
Page 51 and 52: 2.2. Transmission Line Pulsing 35 F
Page 53 and 54: 2.3. Overview of Protection Circuit
Page 61 and 62: 2.4. Dependence of Critical MOSFET
Page 63 and 64: 2.4. Dependence of Critical MOSFET
Page 65 and 66: 2.5. Design Methodology 49 the subs
Page 67 and 68: 2.5. Design Methodology 51 The perf
Page 69 and 70: 2.5. Design Methodology 53 enter se
Page 71 and 72: Chapter 3 Simulation: Methods and A
Page 73 and 74: 3.1. Lattice Temperature and Temper
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3.1. Lattice Temperature and Temper
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3.2. Curve Tracing 65 line (c) in F
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3.3. Mixed Mode Simulation 67 x n-1
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3.3. Mixed Mode Simulation 69 V c C
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3.4. Previous ESD Applications 71 v
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3.4. Previous ESD Applications 73 I
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3.5. Extraction of MOSFET I-V Param
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3.6. Extraction of MOSFET Pf vs. tf
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3.7. Simulation of Dielectric Failu
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Chapter 4 Simulation: Calibration a
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4.1. Calibration Procedure 97 and t
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4.1. Calibration Procedure 99 conta
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4.1. Calibration Procedure 101 4.40
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4.1. Calibration Procedure 103 Afte
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4.1. Calibration Procedure 105 past
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4.1. Calibration Procedure 107 whic
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4.1. Calibration Procedure 109 simu
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4.1. Calibration Procedure 111 (a)
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4.1. Calibration Procedure 113 wher
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4.1. Calibration Procedure 115 peri
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4.1. Calibration Procedure 117 simu
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4.1. Calibration Procedure 119 volt
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4.2. MOSFET Snapback I-V Results 12
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4.2. MOSFET Snapback I-V Results 12
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4.3. Device Failure Results 125 V t
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4.3. Device Failure Results 127 alr
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4.3. Device Failure Results 129 act
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4.3. Device Failure Results 131 (a)
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4.3. Device Failure Results 133 (a)
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4.4. Design Example 135 reached, th
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4.4. Design Example 137 Using value
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Chapter 5 Design and Optimization o
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5.1. Methodology 141 5.1 Methodolog
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5.1. Methodology 143 W L DGS SGS Co
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5.1. Methodology 145 reaches its pe
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5.1. Methodology 147 the same withs
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5.1. Methodology 149 various respon
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5.1. Methodology 151 needed to desc
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5.1. Methodology 153 The actual pat
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5.2. Application 155 To determine h
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5.3. Analysis 157 are flat, a direc
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5.3. Analysis 159 assumed to be iso
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5.4. Optimization 161 Qualitatively
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5.5. Summary of Design Methodology
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Chapter 6 Conclusion In the integra
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6.1. Contributions 167 TLP was show
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6.2. Future Work 169 most ESD quali
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6.2. Future Work 171 Significant wo
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Appendix A Tracer User’s Manual S
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A.3. CONTROL Card 175 A.3 CONTROL C
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A.4. FIXED Card 177 A.4 FIXED Card
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A.5. OPTION Card 179 • DAMP is a
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A.5. OPTION Card 181 A.5.4 Examples
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A.6. SOLVE Card 183 if the voltage
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A.7. Input Deck Specifications 185
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A.9. Examples 187 column contains c
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A.9. Examples 189 fixed num = 1 typ
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A.9. Examples 191 Collector Current
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A.9. Examples 193 title mes.pis mes
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A.9. Examples 195 simulator to use.
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A.9. Examples 197 #Soln #Vctrl Ictr
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Bibliography [1] T.J. Green and W.K
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Bibliography 201 [20] C. Duvvury, R
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Bibliography 203 [42] S.M. Sze, Phy
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Bibliography 205 [63] R. van Overst
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