characterization, modeling, and design of esd protection circuits

20 Chapter 2. ESD Circuit Characterization and Design Issues
+
V i
-
R i =1MΩ
S
DUT
Fig. 2.4 Circuit model for the CDM. A ground pin of the device under
test (DUT) is charged to a voltage V i , after which the switch S
is thrown, removing the voltage source and connecting a
different pin of the device to ground.
while failing another, say the charged-device model [19]. It is even possible for a circuit to
survive one level of a test while failing at a lower level of the same test. One well-known
case is the failure window of the HBM: a device will pass HBM stresses less than 1kV and
greater than 2kV up to 6kV, but will tend to fail at stresses between 1kV and 2kV. Such a
case is described in [20].
There are many limitations to using the classical models to characterize ESD robustness of
circuits. Foremost is that the models offer only restricted insight as to how the protection
circuits work and how and where they fail. The input pulses of the HBM and other models
are complex and very brief, so the response of the circuit is also complex and is hard to
measure. And although the dependence of increased leakage on the test stress level is
tabulated, ESD qualifiers are normally only interested in whether the leakage is above or
below a predefined failure level. In short, the classical models are used as a black box with
a voltage-level stimulus and a simple “pass or fail” response.
Transmission-line pulsing, a relatively new ESD characterization method, provides a way
of opening up this black box. Since this technique was first introduced in 1985 [21] it has
become widely used to characterize and design ESD circuits [4,8,22-24]. A schematic of a
TLP experiment is shown in Fig. 2.5, in which a coaxial transmission line is charged up to
a certain voltage and then discharged into an I/O pin of the device with the ground or
R s
L s