characterization, modeling, and design of esd protection circuits

2.3. Overview of Protection Circuit Design 37
current profiles. The switch S is a normally closed, single-pull double-throw vacuum relay
which is opened and closed by applying and disabling a 12V power supply, respectively.
During a stepped-stress experiment, a leakage measurement between input and ground is
taken after each pulse by switching the input from the transmission line to an ammeter in
series with a VCC supply (not shown in Fig. 2.14). This switching is done with a voltagecontrolled
10GHz coaxial relay placed between the probes and the DUT input. Currently,
an HP3457A multimeter with 1nA resolution is used for leakage measurements, but this
will eventually be replaced by an HP4145 parametric analyzer with 1pA resolution. All
instruments and power supplies are controlled by a personal computer through either a
National Instruments AT-GPIB/TNT IEEE-488 card or a National Instruments PC-DIO-96
digital I/O board. National Instruments’ LabVIEW software package is used to
automatically run a TLP experiment on a test structure and store all I-V and leakage data
from initial device breakdown through device failure. A built-in oscilloscope function
which measures the average height of a waveform in a gated region facilitates the
automatic extraction of the device voltage and current resulting from each input pulse.
2.3 Overview of Protection Circuit Design
This section is not meant to provide an exhaustive review of all types of on-chip
protection but rather to introduce some basic concepts. A thorough discussion of on-chip
protection is presented in [34]. Any I/O protection circuit should provide a low-impedance
path from input to supply during an ESD event to absorb current but provide a very high
impedance during normal operating conditions so as not to affect circuit performance,
e.g., through increased leakage current or parasitic capacitance. Additionally, an ESD
circuit should clamp input voltages at a safe level, i.e., below the dielectric breakdown
voltage of a thin gate transistor. The dielectric threshold electric field is actually time
dependent: it must be held across an oxide for a certain length of time before the oxide
breaks down, as measured by leakage current [40]. The time to breakdown is lower for a
higher stress field. Although the consequences of this time dependence on ESD protection
ability are important, for simplicity we will assume that the voltage across a thin gate must
not exceed some critical level for any amount of time.
When designing ESD protection circuits, there are some important differences to consider
between input protection and output protection. While the high-impedance input pads of a
CMOS chip are connected to the thin gates of the input buffer transistors, the low-