characterization, modeling, and design of esd protection circuits

5.1. Methodology 143
W
L DGS SGS
Contact 1
Poly
Fig. 5.55 Layout of a four-fingered ESD structure showing finger width (W), gate
length (L), and source (SGS) and drain (DGS) contact-to-gate spacing
(actually silicide-to-gate spacing).
reduces the source/drain resistivity to only a few ohms per square. However, in the CMOS
process analyzed here the ESD protection transistors make use of a silicide-blocking
technology to maintain a high value of source/drain resistivity which provides design
flexibility of the ballast resistance (snapback resistance). Several TLP and HBM tests are
run for each structure by testing different die on a wafer or number of wafers. Examples of
the dependence of TLP and HBM withstand levels on layout parameters will be given in
the next subsection.
5.1.2 Correlation of TLP to the Human Body Model
Silicide Block
Active
Transmission-line pulsing provides much insight into device behavior during an ESD
event. Actual circuits, however, must pass qualification using the HBM method of testing.
In order for TLP to provide useful design-related models, the results of TLP must be
correlated to the results of HBM. Although the HBM stress event is characterized by a