characterization, modeling, and design of esd protection circuits

74 Chapter 3. Simulation: Methods and Applications
authors attributed the discrepancy at low times to the two-dimensional nature of the
simulation and the discrepancy at high times to the oversimplified lumped thermal
elements used to model heat conduction through the bottom of the device, leading them to
determine that 2D device simulation is only useful for qualitative studies of thermal
failure. They do not consider that the underestimation of the failure power for short pulse
times may be a result of using the failure criterion of Tpeak > 1688K, which may not be
correct. For instance, it is possible that melting does occur in short-pulse experiments but
that the damage is so localized that the measured increase in leakage is not significant. If
this is the case, then a simulation should not be considered to have reached failure until a
later time, such as when a critical temperature has been exceeded over a “significant”
region of the device.
In contrast to Amerasekera’s results, Diaz found that the simulated failure current, It2 ,
does increase when the contact-to-gate spacing is increased. Vsb and Rsb also increased in
transient simulations when the contact spacing was increased. The conflicting results
between Amerasekera and Diaz are most likely due to the different types of simulations
used, i.e., dc vs. transient, and they underline the importance of considering the time range
of interest when qualifying ESD circuits. The fact that one study found that defining a
critical temperature for failure is valid while the other study found this to be invalid may
also be attributed to the different types of simulations used as well as to the different
thermal boundary conditions used. We can conclude from Amerasekera’s and Diaz’s
studies that defining failure in simulation depends not only upon the type of criteria
chosen but also on the thermal boundary conditions.
3.5 Extraction of MOSFET I-V Parameters
As discussed in Chapter 2, generating an I-V curve using transmission-line pulsing is an
excellent way to study how a device will respond to an ESD stress: the trigger point (Vt1 ,
It1 ) indicates the maximum voltage allowed at the input of the circuit before the protection
device turns on as well as the amount of current needed to turn on the device; the snapback
voltage and snapback resistance determine what the input voltage will be when a given
amount of current is conducting through the device; and the second breakdown point
determines the maximum power the device can absorb before thermal damage is incurred.
All of these circuit parameters can be extracted from device simulations to aid the process
of device design. Three types of I-V curves can be generated from simulation (or from