characterization, modeling, and design of esd protection circuits

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98 Chapter 4. Simulation: Calibration and Results Source Gate Substrate Drain Fig. 4.39 This example of a MEDICI-generated grid shows the concentration of grid points in the channel, LDD, and junction regions. Several microns of the substrate portion of the simulated structure have been omitted in order to display the grid approximately to scale. created by SUPREM-IV has 3827 grid points. Fig. 4.39 shows an example of a MEDICIgenerated grid. For all mobility and impact-ionization model calibration, simulations were run for a 0.5µm-gate structure and a 3.0µm-gate structure to ensure that the models are valid for more than one structure size. Each structure is bounded laterally by the S/D contact edges, with the S/D contact-to gate spacing set equal to that of the test structures. The depth of the device is made large enough that the depletion region does not extend to the bottom edge during any of the simulations. A substrate contact covers this entire bottom edge, neglecting the small substrate resistance between the intrinsic device and the substrate
4.1. Calibration Procedure 99 contact in an actual MOS transistor. The S/D contacts are placed on the top of the structure from the actual contact position all the way up to the spacer edge in order to model the silicide used in the test structures. As mentioned at the beginning of the chapter, the only available test structures with gate-length variations were fully salicided devices. The silicide layer is formed by depositing tungsten or titanium over all active (S/D) areas which reacts with the silicon to form a layer between the S/D contacts and the spacer edge. This layer is a few nanometers deep and has a resistance of a few Ω/❏. Since the silicide’s resistivity is low and it is not used in the structures tested with transmission-line pulsing, the layer is simply approximated by an extension of the metal contacts. 4.1.2 Calibration of MOSFET Characteristics After the correct structure is created, the next phase of calibration is fitting simulated curves to the standard experimental MOSFET characterization curves described in many textbooks [42,61] and depicted in Fig. 4.40. For the AMD structures used in this calibration, data was taken at wafer level using a probe station and HP4145 parametric analyzer. In the simulations, each type of curve is only dependent on certain model parameters. For example, the drain characteristic (Fig. 4.40a) is mainly dependent on parallel-field mobility parameters, while the gate characteristic (Fig. 4.40b) is a function of perpendicular-field mobility parameters. Also, the breakdown voltage (Fig. 4.40e) is determined by the II coefficients of electrons and holes, whereas the substrate current (Fig. 4.40d) really only depends on the electron coefficients since electron current is dominant in this type of stress. Although each curve can be fit individually by calibrating only a few model coefficients, it is important to optimize the mobility and II coefficients over all curves because an ESD event incorporates several physical effects, including junction breakdown, MOSFET action, and bipolar transistor action. Therefore, the philosophy behind the calibration procedure is that separate types of I-V curves can be used to isolate specific model coefficients, but the results of the individual curve fits must yield a set of coefficients which correctly model all device phenomena. Additionally, the calibration should be accomplished while leaving as many model coefficients as possible at their default values, most of which are determined by data published in the literature. Not only does altering a minimum of coefficients save time and effort, it is sensible because although material properties tend to vary across technologies within and between manufacturers, variations in basic physical properties should not be great.
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CHARACTERIZATION, MODELING, AND DES
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Abstract For more than 20 years, su
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Acknowledgments This work could not
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Contents Abstract iii Acknowledgmen
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6 Conclusion 165 6.1 Contributions
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List of Figures 1.1 ESD protection
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3.32 Simulated 1/∆T vs. time and
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A.65 The output file, bvceo.out, fo
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Chapter 1 Introduction Electrostati
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1.1. ESD in the Integrated Circuit
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1.2. Characterizing ESD in Integrat
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1.3. Protecting Integrated Circuits
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1.4. Numerical Simulation 9 simulat
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1.5. Design Methodology 11 process.
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1.6. Outline and Contributions 13 A
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Chapter 2 ESD Circuit Characterizat
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2.1. Classical ESD Characterization
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2.2. Transmission Line Pulsing 19 i
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2.2. Transmission Line Pulsing 21 (
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2.2. Transmission Line Pulsing 23 (
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2.2. Transmission Line Pulsing 25 I
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2.2. Transmission Line Pulsing 27 I
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2.2. Transmission Line Pulsing 29 E
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2.2. Transmission Line Pulsing 31 w
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2.2. Transmission Line Pulsing 33 a
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2.2. Transmission Line Pulsing 35 F
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2.3. Overview of Protection Circuit
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2.4. Dependence of Critical MOSFET
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Page 65 and 66: 2.5. Design Methodology 49 the subs
Page 67 and 68: 2.5. Design Methodology 51 The perf
Page 69 and 70: 2.5. Design Methodology 53 enter se
Page 71 and 72: Chapter 3 Simulation: Methods and A
Page 73 and 74: 3.1. Lattice Temperature and Temper
Page 81 and 82: 3.2. Curve Tracing 65 line (c) in F
Page 83 and 84: 3.3. Mixed Mode Simulation 67 x n-1
Page 85 and 86: 3.3. Mixed Mode Simulation 69 V c C
Page 87 and 88: 3.4. Previous ESD Applications 71 v
Page 89 and 90: 3.4. Previous ESD Applications 73 I
Page 91 and 92: 3.5. Extraction of MOSFET I-V Param
Page 93 and 94: 3.6. Extraction of MOSFET Pf vs. tf
Page 103 and 104: 3.7. Simulation of Dielectric Failu
Page 111 and 112: Chapter 4 Simulation: Calibration a
Page 113: 4.1. Calibration Procedure 97 and t
Page 117 and 118: 4.1. Calibration Procedure 101 4.40
Page 119 and 120: 4.1. Calibration Procedure 103 Afte
Page 121 and 122: 4.1. Calibration Procedure 105 past
Page 123 and 124: 4.1. Calibration Procedure 107 whic
Page 125 and 126: 4.1. Calibration Procedure 109 simu
Page 127 and 128: 4.1. Calibration Procedure 111 (a)
Page 129 and 130: 4.1. Calibration Procedure 113 wher
Page 131 and 132: 4.1. Calibration Procedure 115 peri
Page 133 and 134: 4.1. Calibration Procedure 117 simu
Page 135 and 136: 4.1. Calibration Procedure 119 volt
Page 137 and 138: 4.2. MOSFET Snapback I-V Results 12
Page 139 and 140: 4.2. MOSFET Snapback I-V Results 12
Page 141 and 142: 4.3. Device Failure Results 125 V t
Page 143 and 144: 4.3. Device Failure Results 127 alr
Page 145 and 146: 4.3. Device Failure Results 129 act
Page 147 and 148: 4.3. Device Failure Results 131 (a)
Page 149 and 150: 4.3. Device Failure Results 133 (a)
Page 151 and 152: 4.4. Design Example 135 reached, th
Page 153 and 154: 4.4. Design Example 137 Using value
Page 155 and 156: Chapter 5 Design and Optimization o
Page 157 and 158: 5.1. Methodology 141 5.1 Methodolog
Page 159 and 160: 5.1. Methodology 143 W L DGS SGS Co
Page 161 and 162: 5.1. Methodology 145 reaches its pe
Page 163 and 164: 5.1. Methodology 147 the same withs
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5.1. Methodology 149 various respon
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5.1. Methodology 151 needed to desc
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5.1. Methodology 153 The actual pat
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5.2. Application 155 To determine h
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5.3. Analysis 157 are flat, a direc
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5.3. Analysis 159 assumed to be iso
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5.4. Optimization 161 Qualitatively
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5.5. Summary of Design Methodology
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Chapter 6 Conclusion In the integra
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6.1. Contributions 167 TLP was show
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6.2. Future Work 169 most ESD quali
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6.2. Future Work 171 Significant wo
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Appendix A Tracer User’s Manual S
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A.3. CONTROL Card 175 A.3 CONTROL C
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A.4. FIXED Card 177 A.4 FIXED Card
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A.5. OPTION Card 179 • DAMP is a
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A.5. OPTION Card 181 A.5.4 Examples
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A.6. SOLVE Card 183 if the voltage
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A.7. Input Deck Specifications 185
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A.9. Examples 187 column contains c
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A.9. Examples 189 fixed num = 1 typ
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A.9. Examples 191 Collector Current
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A.9. Examples 193 title mes.pis mes
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A.9. Examples 195 simulator to use.
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A.9. Examples 197 #Soln #Vctrl Ictr
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Bibliography [1] T.J. Green and W.K
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Bibliography 201 [20] C. Duvvury, R
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Bibliography 203 [42] S.M. Sze, Phy
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Bibliography 205 [63] R. van Overst
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