characterization, modeling, and design of esd protection circuits

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118 Chapter 4. Simulation: Calibration and Results V dev / V 25 20 15 10 5 0 + V in - 50Ω 50Ω I dev V dev V dev 0.0 0 5 10 15 20 25 time / ns Fig. 4.44 Device voltage and current vs. time for a transient simulation of the 100/0.75µm structure (cf. Fig. 2.10). Second breakdown is observed at 21ns, corresponding to a peak temperature in the device of 1510K. The simulation circuit is shown inset. relatively high input pulses, a distinct second breakdown was observed, as shown in Fig. 4.44. In the figure, the drop in current and rise in voltage after 3ns are due to the incorrect modeling of the device resistance in the snapback region discussed in the previous subsection. Although the device voltage is too high and the current is too low in the simulation, the power generated in the device is equal to the current-voltage product and thus may still be a reasonable value to use for thermal-failure calibration. In all of the simulations with a second-breakdown time less than 100ns, this time is well defined by a sharp increase in the device current and the peak temperature at this time is around 1500K. The intrinsic carrier concentration at 1500K is about 3X10 18 cm -3 , which approximately equals the doping concentration in the LDD region where the temperature is highest. This result is in agreement with the simple theory of thermal failure which states that a critical temperature, in this case 1500K, defines the onset of second breakdown. Since the drop in I dev 1.0 0.8 0.6 0.4 0.2 I dev / A
4.1. Calibration Procedure 119 voltage and rise in current were more drawn out for failure times greater than 100ns, the time and power to failure (Vdev X Idev ) were defined as the time and power at which the peak temperature reached 1500K. For simulations of the 100/0.75µm structure using the thermal boundary conditions described above, the power to failure for a failure time of 200ns was about 4W. In comparison, the average measured failure power using a 200ns TLP pulse was 11.2W, more than twice the simulated value. This underestimate of the power-to-failure indicates that the modeled heat dissipation was too low, i.e., the thermal resistance was too high, forcing the peak temperature to be too high. Thus, for the next iteration of simulations the lumped thermal resistance was removed from the substrate thermal contact to reduce the device heating. As a result, the power-to-failure at 200ns was increased, but only to about 6W, still almost 50% too low. At this point it was recognized that the absence of heat dissipation to the sides of the simulation structure was incorrect. Since no thermal contacts were placed on the sides of the structure, too much heat was being trapped. In the discussion of the 3D thermal box model (Section 2.2.2), it was explained that the linear extent of thermal equilibrium in an area where heating is time-invariant after time t0 is equal to . Assuming a diffusivity of 0.35cm 2 4πD( t – t0) /s, a time of 200ns corresponds to a distance of about 9.4µm. This is nearly twice the distance from the heat-generation region under the gate to the sides of the standard structure, and thus the lack of thermal contacts on the sides of the structure drastically increases the peak temperature. In light of this calculation, constant-temperature boundary conditions were added to the sides of the simulation structure with no lumped thermal resistance. The lack of thermal resistance is reasonable because the silicon substrate is an effective heat sink and, as shown by the calculation above, the dissipation of heat for the time scale of interest is not affected by a region much greater than the simulation space. In simulations using these boundary conditions, the failure power at 200ns again increased, but only to about 8.0W, still 30% lower than the measured value. If the critical temperature for device failure is redefined as 1688K, the melting point of silicon, the 200ns failure power does increase, but only about 10%, still not enough to compensate for the disparity between simulation and experiment. Since the thermal boundary conditions have been set to maximize heat dissipation, it appears that either 2D simulation is not adequate for quantitatively predicting thermal failure or that the inadequate calibration of the snapback I-V curve for currents well above the snapback point renders proper
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CHARACTERIZATION, MODELING, AND DES
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Abstract For more than 20 years, su
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Acknowledgments This work could not
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Contents Abstract iii Acknowledgmen
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6 Conclusion 165 6.1 Contributions
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List of Figures 1.1 ESD protection
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3.32 Simulated 1/∆T vs. time and
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A.65 The output file, bvceo.out, fo
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Chapter 1 Introduction Electrostati
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1.1. ESD in the Integrated Circuit
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1.2. Characterizing ESD in Integrat
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1.3. Protecting Integrated Circuits
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1.4. Numerical Simulation 9 simulat
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1.5. Design Methodology 11 process.
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1.6. Outline and Contributions 13 A
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Chapter 2 ESD Circuit Characterizat
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2.1. Classical ESD Characterization
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2.2. Transmission Line Pulsing 19 i
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2.2. Transmission Line Pulsing 21 (
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2.2. Transmission Line Pulsing 23 (
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2.2. Transmission Line Pulsing 25 I
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2.2. Transmission Line Pulsing 27 I
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2.2. Transmission Line Pulsing 29 E
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2.2. Transmission Line Pulsing 31 w
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2.2. Transmission Line Pulsing 33 a
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2.2. Transmission Line Pulsing 35 F
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2.3. Overview of Protection Circuit
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2.4. Dependence of Critical MOSFET
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2.4. Dependence of Critical MOSFET
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2.5. Design Methodology 49 the subs
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2.5. Design Methodology 51 The perf
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2.5. Design Methodology 53 enter se
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Chapter 3 Simulation: Methods and A
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3.1. Lattice Temperature and Temper
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3.2. Curve Tracing 65 line (c) in F
Page 83 and 84: 3.3. Mixed Mode Simulation 67 x n-1
Page 85 and 86: 3.3. Mixed Mode Simulation 69 V c C
Page 87 and 88: 3.4. Previous ESD Applications 71 v
Page 89 and 90: 3.4. Previous ESD Applications 73 I
Page 91 and 92: 3.5. Extraction of MOSFET I-V Param
Page 93 and 94: 3.6. Extraction of MOSFET Pf vs. tf
Page 103 and 104: 3.7. Simulation of Dielectric Failu
Page 111 and 112: Chapter 4 Simulation: Calibration a
Page 113 and 114: 4.1. Calibration Procedure 97 and t
Page 115 and 116: 4.1. Calibration Procedure 99 conta
Page 117 and 118: 4.1. Calibration Procedure 101 4.40
Page 119 and 120: 4.1. Calibration Procedure 103 Afte
Page 121 and 122: 4.1. Calibration Procedure 105 past
Page 123 and 124: 4.1. Calibration Procedure 107 whic
Page 125 and 126: 4.1. Calibration Procedure 109 simu
Page 127 and 128: 4.1. Calibration Procedure 111 (a)
Page 129 and 130: 4.1. Calibration Procedure 113 wher
Page 131 and 132: 4.1. Calibration Procedure 115 peri
Page 133: 4.1. Calibration Procedure 117 simu
Page 137 and 138: 4.2. MOSFET Snapback I-V Results 12
Page 139 and 140: 4.2. MOSFET Snapback I-V Results 12
Page 141 and 142: 4.3. Device Failure Results 125 V t
Page 143 and 144: 4.3. Device Failure Results 127 alr
Page 145 and 146: 4.3. Device Failure Results 129 act
Page 147 and 148: 4.3. Device Failure Results 131 (a)
Page 149 and 150: 4.3. Device Failure Results 133 (a)
Page 151 and 152: 4.4. Design Example 135 reached, th
Page 153 and 154: 4.4. Design Example 137 Using value
Page 155 and 156: Chapter 5 Design and Optimization o
Page 157 and 158: 5.1. Methodology 141 5.1 Methodolog
Page 159 and 160: 5.1. Methodology 143 W L DGS SGS Co
Page 161 and 162: 5.1. Methodology 145 reaches its pe
Page 163 and 164: 5.1. Methodology 147 the same withs
Page 165 and 166: 5.1. Methodology 149 various respon
Page 167 and 168: 5.1. Methodology 151 needed to desc
Page 169 and 170: 5.1. Methodology 153 The actual pat
Page 171 and 172: 5.2. Application 155 To determine h
Page 173 and 174: 5.3. Analysis 157 are flat, a direc
Page 175 and 176: 5.3. Analysis 159 assumed to be iso
Page 177 and 178: 5.4. Optimization 161 Qualitatively
Page 179 and 180: 5.5. Summary of Design Methodology
Page 181 and 182: Chapter 6 Conclusion In the integra
Page 183 and 184: 6.1. Contributions 167 TLP was show
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6.2. Future Work 169 most ESD quali
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6.2. Future Work 171 Significant wo
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Appendix A Tracer User’s Manual S
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A.3. CONTROL Card 175 A.3 CONTROL C
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A.4. FIXED Card 177 A.4 FIXED Card
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A.5. OPTION Card 179 • DAMP is a
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A.5. OPTION Card 181 A.5.4 Examples
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A.6. SOLVE Card 183 if the voltage
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A.7. Input Deck Specifications 185
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A.9. Examples 187 column contains c
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A.9. Examples 189 fixed num = 1 typ
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A.9. Examples 191 Collector Current
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A.9. Examples 193 title mes.pis mes
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A.9. Examples 195 simulator to use.
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A.9. Examples 197 #Soln #Vctrl Ictr
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Bibliography [1] T.J. Green and W.K
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Bibliography 201 [20] C. Duvvury, R
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Bibliography 203 [42] S.M. Sze, Phy
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Bibliography 205 [63] R. van Overst
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