Manual - 8500A Series Peak Power Meter - Giga-tronics

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4 Theory of Operation 4.1 Introduction This chapter presents a functional description of the electrical assemblies in the Model 8501A and 8502A Peak Power Meters (PPM). Table 8-1 in Chapter 8 lists the circuit assemblies by reference designation and includes the schematic diagram and assembly number for each board. Schematic diagrams and component layouts are in Chapter 8. The method to properly ground all PC boards is common throughout the PPM. Each PC board contains both input and output isolator stages to transfer the reference or ratio common ground when signals are passing between the PC boards to an on-board common ground. When any signals leave the boards, they pass through another isolator stage, which transfers them back to the between-the-boards reference ground. 4.2 System Description The following is a general description of the PPM circuit, with reference to Figure 4-1. The detected RF signal enters the PPM as an analog voltage and is received by the circuits of the Analog PC board (A6/A7). The single channel Model 8501A uses only A6 whereas the dual channel 8502A uses both A6 and A7. Both boards are identical. The Analog board circuits use an RC network to compensate the signal for frequency dependent losses in the delay line. The signal is sampled and held until the completion of the data conversion cycle. A/D conversion occurs to supply digital data to the Central Processing Unit (CPU). The Trigger Amplifier of the Analog board senses the detector output voltage before it reaches the Delay Line. It uses the signal to provide an Internal Trigger, controlled and conditioned by the A5 Digital Delay board, when the internal trigger is selected. The Peripheral Interface circuits interface read and write signals under the control of the CPU board. The Analog board also receives temperature information sensed by the thermistor in each detector. The programmable delay function of the A5 Digital Delay board establishes the time delays when measuring RF pulses. Trigger inputs can come from either the CPU (internal), through the Trigger Amplifier, from the pulse itself as it is detected, or from an external source connected to the rear panel of the instrument. The Delay board also supplies a synchronized output signal to a rear panel connector for an external meter to read the pulse at the point where the sample is taken. The A4 CPU board provides (through the CPU Bus Line) the interface between the other PC boards, and generates all of the control signals for timing and controlling the various functions of the boards. Apart from the bus, the CPU has two other lines from the power supply and the delay board. These inputs tell the CPU if there has been a power failure of any kind, and when it should halt its activity until a sample of the incoming pulse is taken. This allows the sample to be unaffected by CPU generated interference. The A9 Keyboard and A10 Display PC boards interface keystroke and hand wheel movement information, and display indication signals to and from the front panel components. These functions are controlled by the A8 Front Panel Interface board, which is controlled by the CPU. The front panel interface also has a Manual No. 20790, Rev C, November 1998 4-1 Superceded by Revision D, March 2009
Series 8500A Peak Power Meters high voltage switching power supply for the Electro-Luminescent (EL) display. The Ready and New Data lights on the front panel are turned on and off by control signals sent through A9 from the delay board. The A3 GPIB/Cal Control board provides the interface to the GPIB, and contains the circuitry required for controlling the operation of the automatic detector Calibrator (A12). It also interfaces with the PROMs in the detectors, contains the sound generator circuits, and provides an RF blanking output to turn off RF power when zeroing the instrument. The A12 Calibrator assembly contains the 1 GHz Programmable Calibration Source that furnishes a precise signal for automatic calibration of the PPM detectors. MODEL 8502A: Channel A shown; Channel B is identical DETECTOR ASSY COMP NET A6/A7 KEYBOARD A8 Delay Line RF Input DETECTOR Therm SAMPLE/HOLD A/D CONVERTER A6/A7 Sample Pulse GPIB INTERFACE A3 GPIB Input/ Output TRIG AMP A6/A7 Int Ext PROGRAMMABLE DELAY A5 CPU PROGRAMMABLE INTERFACE A6/A7 A4 CPU BUS DISPLAY Trigger Input A10 (thru A8) Calibrator 1 GHz Output 1GHz PROGRAMMABLE CALIBRATION SOURCE A12 CALIBRATOR CONTROLLER A3 Figure 4-1. Series 8500A System Block Diagram 4-2 Manual No. 20790, Rev C, November 1998 Superceded by Revision D, March 2009
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Manual - 8500A Series Peak Power Meter - Giga-tronics

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