Manual - 8500A Series Peak Power Meter - Giga-tronics

Theory of Operation
minus the set value. The trigger level is determined by the Trig Level Bus. It requires 10 bits of data
which are sent from U6 port C and U7 ports C0 and C1. The trigger is selected by Trig Select 0 and Trig
Select 1 from U7 ports C2 and C3. The delay board’s interrupt acknowledgment, New Data Ack, comes
from U7 port C7.
The Load, Reset, and CPU Halt signals are generated by U1, U2, and U3. If U2 multiplexes U7 ports C2
and C3 into the Y0 line, it tells the circuit to do nothing. Into the Y1 line means to reset, into the Y2 line
tells it to load, and into the Y3 line indicates Halt Enable. To set the Halt signal, Halt Enable sets the
latch U3A. Then, when Y1 is addressed, the following will happen:
1. The monostable pulse generator, U1, will generate a reset signal at the point where the negative
edge of the signal at Y1 occurs.
2. After that, the positive edge of the signal at Y1 will clock U3B which will produce the Halt
signal.
The Halt function will be reset by a signal through the Sample 2 line. If no sample has been
triggered, it can be reset by the CPU Reset or the interrupt requests corresponding to data
received from the keyboard or through the GPIB. This is done by resetting latches U3A and
U3B. The Reset also activates the Software Trigger. This will be ignored by the delay circuits
unless soft trigger has been selected.
Trig Threshold
The Trig Threshold circuit sets the level for the internal Trig Comparators. It accepts data from the Trig
Level Bus, and produces a voltage between 0 and 2.5 V, which is sent to the comparators.
The Trig Threshold circuitry consists of the 10-bit DAC, U40, amplifier U41B, and associated
components. Its output is determined by the data present on the Trig Level Bus, and can be monitored at
TP15. The amplitude range is 0 to 10.23 V with 10 mV resolution. Registers R16 and R17 form a voltage
divider to give a level between 0 and 2.56 V which is sent to the Trig Comparators.
Internal Trig Comparators
The Internal Trig Comparators consist of one fast comparator each for channel A and channel B Internal
Trigger Signals. The comparators also contain over-voltage protection at each of the inputs to protect
them against voltages higher than a maximum of 3.0 V.
The Internal Trig Comparators function is accomplished by using one dual, fast ECL output comparator.
Its recommended maximum input voltage is 3 V. Each input is protected against over-voltage by an
identical circuit. On channel A, the input is connected to the emitter of Q13. The base of Q13 is
connected to 2.1 V which is derived from the +15 V supply through R8 and R9. When the voltage is
greater than 2.1 V plus the VBE(ON) of Q13, Q13 will then have a low resistance to ground that will
serve to limit the comparator input voltage. The non-inverted outputs of the channel A and channel B
comparators can be monitored at TP14 and TP15.
Trig Select
The Trig Select is a digital multiplexer that selects either the Internal trigger from channel A or B, a
software trigger generated by the CPU, or an external trigger from a source connected to the instrument
rear panel, all controlled through the CPU interface.
The Trig Select circuitry consists of an ECL 4-wide 4-3-3-3 input, AND/OR gate U30, and a TTL-ECL
translator, U31, for the trigger select lines. The trigger inputs are active lows, and are selected when the
two remaining inputs of the OR gate are low. The output goes low when the selected trigger input goes
low.
Manual No. 20790, Rev C, November 1998 4-15
Superceded by Revision D, March 2009