Manual - 8500A Series Peak Power Meter - Giga-tronics

Series 8500A Peak Power Meters
Ramp Control Logic
The Ramp Control Logic controls the sequence of events that are required to generate the selected time
delay. The Reset input enables the circuit to accept the first positive edge from the trigger pulse. The ON
1 input accepts the trigger pulse to turn on the Ramp Generator, enable the Counter, and to initiate the
Voltage Hold. The OFF 1 input, consisting of the first negative edge of the clock signal after the trigger,
turns off the Ramp Generator and enables the Clock Gate. The ON 2 signal comes from the Counter’s
count output and turns on the Ramp Generator. The OFF 2 signal consists of the Sample Comparator
output which turns off the Ramp Generator when the sample is taken.
TP1 can be used as an oscilloscope trigger when testing the Delay board.
Zero to 25.5 ns Delay
This circuit consists of a DAC controlled by the Delay DAC Bus through the CPU Interface circuitry. It
sets the proper levels for a delay between 0 and 25.5 ns with an accuracy of 0.1 ns. Its output goes to the
Sample Comparator.
The 0 to 25.5 ns Delay is set by the 8-bit DAC U35 and amplifier U32B. The output is biased by R37
from the +10 V reference, and has a range of -0.5 V to +0.994 V full scale with 5.86 mV resolution. The
output voltage can be measured at TP6.
Pulse Shaper
The Pulse Shaper is triggered by the Sample Comparator and provides the sample signals to the samplers
on the analog boards. It also provides a synch signal to the rear panel SYNCH OUTPUT connector of the
instrument. The synch signal is simultaneous with the 15 ns wide Sample 1 signal. The Sample 2 signal
is also used in the CPU Interface to end the halt signal to the CPU. Sample 2 also goes to the Interrupt
Latch and the Delay board Reset Latch to prevent any triggering from occurring until after the delay
board has been reset.
The Pulse Shaper consists of an ECL monostable multivibrator, U38, which will provide a 15 ns pulse.
U35 provides buffered differential outputs to the Sample 1 line and the Synch Out signal. U22 provides a
4.3 ms Sample 2 pulse.
Interrupt Latch
The Interrupt Latch output goes directly to the CPU interrupt request input to alert the CPU that a sample
has been taken. It is reset by the New Data Ack signal coming from the CPU Interface when the analog
board has finished with the sampled voltage.
The Interrupt Latch consists of a D-type flip-flop, U17B. It is clocked by the Sample 2 line to produce an
interrupt request New Data signal to the CPU, and is reset through the New Data Ack. line.
4-18 Manual No. 20790, Rev C, November 1998
Superceded by Revision D, March 2009