Manual - 8500A Series Peak Power Meter - Giga-tronics

Series 8500A Peak Power Meters
feedbacks. If the routine is in a mode where several samples are being averaged, the first sample will be
in the autorange mode and be amplified by the selected gain.
When autoranging is inactive (latch output is high impedance), the latch interfaces with outputs from the
CPU to allow the CPU to control the gain. This mode is used during calibration or self test to allow the
gain to be manually selectable.
U19 is a filter that can be selected to be either in or out of the gain loop. In the CW mode it is in the
loop, but in the pulse mode it is not used to allow for a faster settling time during the analog to digital
conversion. U19 is switched in or out of the loop by U15A.
U16 is an integrated sample and hold amplifier directly controlled by the status signal from the U7 A/D
converter. When U7 is given the command to convert, the status signal goes active and stays active until
the conversion has completed. Then U17B, C, and D rectify the signal to give a positive output that is
sent to one of the inputs of the U6 latch. Input 2D1 of U6 determines the positive or negative status of
the signal. U7 interfaces directly to the data bus, and has a built-in 10 V voltage reference used
throughout the system. R13 adjusts the value of the 10 V reference.
The thermistor interface circuit, U21B, uses the resistance of the detector’s thermistor in conjunction with
the 10 V reference to determine the temperature of the detector diodes. This output is then sent to the
U20 multiplexer.
U8 is a 12 bit DAC. U21 gives a fixed offset so that there will be a resolution of exactly 2 mV
corresponding to 0.02 dB when R47 is adjusted to the proper gain setting. The total range is from +30 to
-50 dBm.
Refer to sheet 2 of schematic diagram #20742. The board first has an RC network that compensates for
the frequency dependent losses in the delay, to assure correct pulse response. The signal is sent from the
board to the delay line. Sheet 2 also shows the buffer amplifiers used with the trigger signals and monitor
outputs. The input to these amplifiers comes from the detector output voltage before it reaches the delay
line (at the point where the detector cable interfaces with the instrument). PPI U1 has all of the output
control signals and status inputs as well as an interface to the CPU bus.
The trigger amplifier consists of OpAmp U30, high speed buffer U31, analog switch U32, and peripheral
circuitry. U30 and U31 form a composite amplifier with U31 transmitting the ac information through
C106, and U30 transferring the dc information through R165. R113 adjusts the dc offset of U30. Analog
switch U32 sets the gain of U30 either to unity or to 10. In the X10 gain range the rise time of the
trigger signal is slower. The monitor output is taken from U33, and is not corrected for offset.
U2A, B, C & D and U3A, B, C & D are the final address decoders. The chip select line, the Address line
(A14), and data strobes choose whether to activate the A to D or D to A converter, or to activate PPI U1
which is controlled by the data bus and will interface read or write signals through the A1 and A2 lines.
Sheet 3 of DWG# 20742 shows the voltage input and grounding configurations for all of the IC’s on the
Analog PC board.
4-22 Manual No. 20790, Rev C, November 1998
Superceded by Revision D, March 2009