Manual - 8500A Series Peak Power Meter - Giga-tronics

Theory of Operation
The positive edge of the Delay Reset signal at U17A pin 11 will clock the Delay Reset Latch whose
output will enable the Ramp Control Logic, the Ramp Generator, and the Sample Comparator. The reset
input of the ramp control flip-flops (pin 13 of U29A and U29B) is released so that another trigger input
can be accepted. The Ramp Generator switch, U33C, that is holding the output voltage at its initial value
will open and the Sample Comparator latch, U34, will be released.
At the time the trigger pulse occurs, the Pulse Stretcher will ensure that only the first positive edge of the
pulse will be able to trigger the Ramp Control Logic. The ON 1 input will clock flip-flop U29A and its
output (monitored at TP1) will then activate the following events:
A. Turn on the Ramp Generator.
B. Trigger the Voltage Hold circuit to take a 3.3 microsecond duration sample of the Ramp Generator’s
output voltage and then to hold it.
C. Enable the Ramp Control Logic flip-flop, U25B so that it can accept the Clock signal for the
required timing.
D. Enable the U14 counter.
The first positive edge of the pulse from the Clock-inverted output at U23B pin 14 will time flip-flop
U25B to turn off the Ramp Generator and also to enable the Clock Gate. The Ramp Generator output
voltage will then remain stable while the Voltage Hold function is taking a sample of it. The next clock
pulse then starts the Counter counting down. When it has counted down to zero, it will cause an inverted
clock pulse to be gated at its output, U24A pin 6, which will in turn clock flip-flop U25A to turn on the
Ramp Generator.
As the output voltage reaches the level determined by the selected delay, the Sample Comparator U34
will flip and trigger the Pulse Shaper to produce the sample pulses. The output will also turn off the
Ramp Generator by resetting U25A in the Ramp Control Logic circuit. The Sample 2 leading edge then
sets the Delay board Reset Latch and the Interrupt Latch, and resets the CPU Interface Halt signal. When
the instrument is first powered on, the Delay board Reset Latch is set by the Load signal because no
Sample 2 signal is generated at that time.
Activation of the Delay board Reset Latch will then cause the following events:
1. The Ramp Control Logic flip-flops, U25B and U29A, will be reset.
2. The Ramp Generator output voltage will be reset to +3 V.
3. A ready signal will be sent to the front panel Ready lamp.
After the CPU has processed the requested interrupt, it will send a New Data Ack signal to reset the
Interrupt Latch and the Voltage Hold circuits.
A very important function in the operation of the delay board is the ability to precisely set a delay using
a very stable clock with a frequency lower than the resolution of the board, and still be able to accept
trigger signals that are not in synch with the clock. As can be seen on the Ramp Output Voltage timing
line in Figure 4-6, the time A from the trigger to the negative clock edge plus the time B from the count
out negative edge to the set threshold point is always the same. This is one clock period plus the fine
delay set by the 0 to 25.5 ns Delay DAC plus eventual gate and other delays. These delays are
independent of the exact timing between the trigger signal and the clock.
Manual No. 20790, Rev C, November 1998 4-13
Superceded by Revision D, March 2009