Manual - 8500A Series Peak Power Meter - Giga-tronics

Series 8500A Peak Power Meters
Address) outputs are used in this protocol. There is an external input to the VPA, and the VPA is also
used in the interrupt process.
NAND gate U20A and inverter U40A provide an active low signal when a device outside the buffers is
addressed.
Unbuffered Memory
The memory inside the buffers consists of two 8Kx8 bits of RAM and two 32Kx8 bits of ROM with the
RAMs kept alive by a battery when the instrument is turned off. NAND gate U26D (also battery
powered) is deselected by the AC FAIL signal when the instrument is off to protect the contents of the
memory. Each pair of memories use the 16-bit wide data bus and are addressed with one device select
signal. The upper and lower data bytes are selected in OR gate U14 by letting the Upper Data Strobe
(UDS) and Lower Data Strobe (LDS) gate the R/W output from the MPU to produce the Lower data
Write Enable (L.WE), Upper data Write Enable (U.WE), Lower data Output Enable (L.OE), and Upper
data Output Enable (U.OE) signals.
Reset Timer
The U17 reset timer consists of a 555 monostable pulse generator. When the instrument is turned on or
when the reset button on the back panel is pressed it generates a 0.5 second pulse to reset the MPU.
U22A & B give separate open collector inputs to the RESET and HALT inputs. U22C provides the HALT
signal which comes from the Delay board. The RESET pin of the MPU is a bidirectional line, and the
MPU can generate its own resets. Diode CR1 enables the AC Fail to Halt the MPU. This is necessary to
ensure that the MPU is not trying to make a data transfer to the non-volatile RAMs or Real Time Clock
when they are being deselected by the AC Fail signal.
Interrupt Priority Decoder
The U37 Interrupt Priority Decoder interfaces the three interrupt priority lines (IPL0, IPL1, and IPL2) to
the seven interrupt request lines (IRQ1 through IRQ7). The three output lines of U37 will have encoded
the number of the highest priority input line that has been driven low. As can be seen on the schematic,
the AC Fail line is connected to the highest priority interrupt input. The lowest priority interrupt input is
connected to the Real Time Clock for timed interrupts.
Data Buffers
Data buffers U7, U8, U9, U13, U32, and U33 give an increased drive capability to all of the signals on
the CPU bus that require the increased capacity. They are enabled by U40A from the Address Decoder
circuit. This will happen each time none of the Unbuffered Memories have been selected. The R/W signal
determines the direction of data flow in the bidirectional buffers used with the data bus lines.
External Memory
The External Memory interfaces the buffered CPU bus. It consists of two pairs of 8Kx8 bits of RAM
(U5, U6, U30, and U31), and three pairs of 32Kx8 bits of ROM (U2, U3, U4, U27, U28, and U29).
Real Time Clock
The Real Time Clock, U1, interfaces the Buffered CPU bus. Data transfer follows the 6800 compatible
protocol with the E and VMA signals to produce the handshaking required for the transfer. U23A & B,
U24A & B, U25B and U26B control U1. To see the timing used in the data transfer, it is recommended
that the manufacturer’s data sheet for U1 (Motorola Type MC-146818P) be consulted. C47 adjusts the
frequency of the internal clock of U1. The 32.768 kHz frequency can be monitored at TP6. The Real
Time Clock also provides a timed Interrupt Request signal (IRQ1) used by the CPU operating system. Its
frequency is software programmable, and can be monitored at TP7. The Real Time Clock is deselected by
the AC Fail line through U26B.
4-10 Manual No. 20790, Rev C, November 1998
Superceded by Revision D, March 2009