Manual - 8500A Series Peak Power Meter - Giga-tronics

Theory of Operation
The signal from the delay line is applied to a fast sample and hold circuit (CR16 to 19 and U29) with a
sample pulse width of 15 ns. Next is a second sample and hold circuit (U28) with a pulse width of
approximately 4 µs. The second sample and hold circuit is to ensure that the sampled signal that is
present will not change in amplitude while it is being held. The signal is held during the time from when
the sample is taken to the completion of the data conversion cycle. U28 can either use the sampled signal,
or take the signal directly from the input without using the sampling circuitry.
There are four stages of gain available after the signal reaches U28. The gain can be either 1 or 8 through
each stage. The circuits are composed of U27 with a fixed gain of 2, amplifier U26, U18, low pass filter
U19, U11 which is the third gain stage, and U12 which is the amplifier for the fourth gain stage. All four
stages are used only in the CW mode and give a total gain of just over 8,000. In the peak pulse mode the
last two amplifiers (U11 and U12) are not used, so the total gain will be 64.
After the four gain stages, there is a multiplexer circuit that allows the selection of either the measured
signal from the detector or the voltage from the thermistor in the detector. U21B will generate a voltage
proportional to the thermistor temperature. This voltage goes to U20, and then to the ADC.
U16, U17A, B & C, and U9 comprise a circuit that will give the absolute value and determine the
polarity sign of the signal. U16 ensures that the voltage is steady during the conversion time. It receives
the status (when conversion is occurring) from A to D converter U7. The D to A conversion circuit
formed by U8, U14A, and U21A give an analog output proportional to the power level being sensed by
the detector.
The system 10 V reference voltage comes from the U7 A to D converter. U14C gives the +10 V
reference, and U14B gives the -10 V reference. During the automatic self test routine of the instrument,
the signal from the DAC (U8, U14, and U21) is tested to assure that these components are operating
properly.
As an example of signal flow through the analog circuitry, when the first signal sample is directed to the
fast sample and hold circuit, it comes in through the Sample 1 line (on the left side of the schematic) as a
balanced ECL signal, and then goes to differential receiver Q2 and Q3.
When a trigger is sent, Q2 produces a current pulse to trigger blocking oscillator Q4. The blocking
oscillator generates a 20 V pulse approximately 30 ns long at the secondary of T1. This pulse overcomes
the reverse bias normally applied to the sampling bridge (CR16 - CR18), and drives a heavy current
through it, thus connecting sampling capacitor C72 to the input signal during the sampling interval.
R120 gives a controlled discharge of C72 between the samples. This is done so that whenever a sample is
to be taken, C72’s voltage is close to zero to set it to the same condition for each of the samples. The
reason for this is to assure repetitive accuracy for every sample of the specific signal being measured.
U29 is a high impedance amplifier.
The second signal sample comes into the board through the line labeled Sample 2, and goes to a circuit
which includes switch U25D, holding capacitor C70, and isolation amplifier U28. R136 serves the same
purpose as R120 (to control C70’s discharge). Setting the zero (or close to zero) dc offset level required
while sampling is in progress is controlled at R112 (Sample Zero), and can be monitored at TP5.
Selection between the CW or peak power mode signals is through the U25A & B switches. U25A & B
can also select the +15 V signal through U13A. This allows the gain of the various stages to be separately
checked using a known input. U27 has a fixed gain of 2. U25C (on the negative input of U27) is
permanently closed, and improves the common mode rejection of the amplifier.
Each of the four selectable gain stages are identical. The first is a comparator (U23) where the input
signal is compared with a fixed level. Then, the signal from each of the stages is sent to the U6 latch. U6
can operate in several different modes. When measurements are being taken, the latch is in the
autoranging mode. This means that the inputs for the latch are the signals from the comparators. The
outputs, which directly follow the inputs in the autoranging mode, are controlling the switch and the gain
circuits. The first gain stage, U22A, determines whether the gain will be 1 or 8 by selecting different
Manual No. 20790, Rev C, November 1998 4-21
Superceded by Revision D, March 2009