Xilinx Constraints Guide

DRIVE (Drive)
The DRIVE (Drive) constraint:
Architecture Support
Applicable Elements
• Is a basic mapping directive
Chapter 4: Xilinx Constraints
• Selects the output for drive strength for all supported FPGA architectures.
• Selects output drive strength (mA) for the SelectIO technology buffers that use
the LVTTL, LVCMOS12, LVCMOS15, LVCMOS18, LVCMOS25, or LVCMOS33
interface I/O standard
Applies to FPGA devices. Does not apply to CPLD devices.
This constraint may be used with an FPGA device in one or more of the following design
elements, or categories of design elements. Not all devices support all elements. To see
which design elements can be used with which devices, see the Libraries Guides. For
more information, see the device data sheet.
• IOB output components (such as OBUF and OFD)
• SelectIO technology output buffers with:
– IOSTANDARD = LVTTL
– LVCMOS15
– LVCMOS18
– LVCMOS25, or
– LVCMOS33
• Nets
Propagation Rules
DRIVE is illegal when attached to a net or signal, except when the net or signal is
connected to a pad. In this case, DRIVE is treated as attached to the pad instance. When
attached to a design element, DRIVE is propagated to all applicable elements in the
hierarchy below the design element.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
• Attach to a valid IOB output component
• Attribute Name
DRIVE
• Attribute Values
For a list of the constraint values, see the UCF and NCF Syntax section below.
Constraints Guide
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