Xilinx Constraints Guide

Example One
Chapter 4: Xilinx Constraints
Place the memory in the SLICE_X1Y1. SLICE_X1Y1 is in the lower left corner of the
device. You can apply a single-SLICE constraint such as this only to a 16 x 1 or 32 x 1
memory.
Schematic LOC=SLICE_X1Y1
UCF INST “/top-7/rq” LOC=SLICE_X1Y1;
Example Two
Place the memory in either SLICE_X2Y4 or SLICE_X7Y9.
Schematic LOC=SLICE_X2Y4, SLICE_X7Y9
UCF INST “/top-7/rq” LOC=SLICE_X2Y4,
SLICE_X7Y9;
Example Three
Do not place the memory in column of slices whose X coordinate is 5. You can use the
wildcard (*) character in place of either the X or Y coordinate value in the SLICE name to
specify an entire row (Y*) or column (X*) of slices.
Schematic PROHIBIT SLICE_X5Y*
UCF CONFIG PROHIBIT=SLICE_X5Y*;
Block RAM (RAMBs) Constraint Examples
This section applies to FPGA devices
Block RAM constraints can be assigned from the schematic or through the UCF file.
From the schematic, attach the LOC constraints to the block RAM symbol. The
constraints are then passed into the netlist file. After mapping they are read by PAR.
For more information on attaching LOC constraints, see the application user guide.
Alternatively, in the constraints file a memory is identified by a unique instance name.
Spartan-3 and Higher Devices
An FPGA block RAM has a different XY grid specification than a slice or multiplier. It is
specified using RAMB16_Xm Yn where the X and Y coordinate values correspond to
the block RAM grid array. A block RAM located at RAMB16_X0Y1 is not located at the
same site as a flip-flop located at SLICE_X0Y1.
For example, assume you have a device with two columns of block RAM, each column
containing two blocks, where one column is on the right side of the chip and the other is
on the left. The block RAM located in the lower left corner is RAMB16_X0Y0. Because
there are only two columns of block RAM, the block located in the upper right corner
is RAMB16_X1Y1.
Schematic LOC=RAMB16_X0Y0 (for all FPGA devices
except Virtex-5 devices)
LOC=RAMB36_X0Y0 (for Virtex-5 devices)
UCF INST “/top-7/rq” LOC=RAMB16_X0Y0;
Slice Constraint Examples
This section applies to all FPGA devices These are currently the only architectures that
use the slice-based XY grid designations.
Constraints Guide
UG625 (v. 13.2) July 6, 2011 www.xilinx.com 167