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Xilinx Constraints Guide

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Falling Edge <strong>Constraints</strong><br />

Chapter 4: <strong>Xilinx</strong> <strong>Constraints</strong><br />

The falling edge OFFSET IN constraint defines the time that the data becomes valid<br />

prior to falling clock edge used to capture the data. In this example, the data becomes<br />

valid 250 ps after the falling clock edge. This results in an OFFSET IN BEFORE value<br />

of -250 ps with the value negative because it begins after the clock edge. Once the data<br />

begins, it remains valid for 2 ns. This results in a VALID value of 2 ns. The FALLING<br />

keyword is used with this constraint to indicate that the constraint applies to only the<br />

falling edge synchronous elements, and that the OFFSET IN BEFORE value is specified<br />

to the falling clock edge.<br />

For more information about the RISING and FALLING keywords, see the Timing<br />

<strong>Constraints</strong> User <strong>Guide</strong>.<br />

UCF Syntax<br />

The complete UCF syntax of the clock PERIOD and OFFSET IN constraint for the<br />

example is shown below.<br />

NET “clock” TNM_NET = CLK;<br />

TIMESPEC TS_CLK = PERIOD CLK 5.0 ns HIGH 50%;<br />

OFFSET = IN -250 ps VALID 2 ns BEFORE clock RISING;<br />

OFFSET = IN -250 ps VALID 2 ns BEFORE clock FALLING<br />

UCF Source Synchronous DDR Center Aligned Example<br />

The Source Synchronous Dual Data Rate (DDR) Center aligned case consists of an<br />

interface where the clock is sent from the transmitting device aligned with the center of<br />

the data. In a dual data rate interface, data is captured with both the rising and falling<br />

clock edges. In the DDR case, separate OFFSET IN constraints must be defined for<br />

the rising and falling clock edge registers capturing the data. Using the RISING and<br />

FALLING keywords with the OFFSET IN constraint simplifies this task.<br />

Example Waveform<br />

In this example a dual data rate interface is shown with a clock period of 5 ns and 50/50<br />

duty cycle. The rising and falling data is valid for 2 ns and is centered over the high and<br />

low clock edges. This results in a 250 ps margin before and after data valid window.<br />

Rising Edge <strong>Constraints</strong><br />

The rising edge OFFSET IN constraint defines the time that the data becomes valid prior<br />

to rising clock edge used to capture the data. In this example, the data becomes valid 1 ns<br />

before the rising clock edge. This results in an OFFSET IN BEFORE value of 1 ns with the<br />

value positive because it begins before the clock edge. Once the data begins, it remains<br />

valid for 2 ns. This results in a VALID value of 2 ns. The RISING keyword is used with<br />

this constraint to indicate that the constraint applies to only the rising edge synchronous<br />

elements, and that the OFFSET IN BEFORE value is specified to the rising clock edge.<br />

Falling Edge <strong>Constraints</strong><br />

The falling edge OFFSET IN constraint defines the time that the data becomes valid<br />

prior to falling clock edge used to capture the data. In this example, the data becomes<br />

valid 1 ns before the falling clock edge. This results in an OFFSET IN BEFORE value<br />

of 1 ns with the value positive because it begins before the clock edge. Once the data<br />

begins, it remains valid for 2 ns. This results in a VALID value of 2 ns. The FALLING<br />

keyword is used with this constraint to indicate that the constraint applies to only the<br />

falling edge synchronous elements, and that the OFFSET IN BEFORE value is specified<br />

to the falling clock edge.<br />

<strong>Constraints</strong> <strong>Guide</strong><br />

UG625 (v. 13.2) July 6, 2011 www.xilinx.com 197

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