Xilinx Constraints Guide

Example
Chapter 3: Timing Constraint Strategies
In this example two unrelated clocks enter the FPGA device through separate external
pins. The first clock, CLKA, is the source clock, and the second clock, CLKB is the
destination clock. The circuit for this example is shown in the following figure:
NET “CLKA” TNM_NET = FFS “GRP_A”;
NET “CLKB” TNM_NET = FFS “GRP_B”;
TIMESPEC TS_Example = FROM “GRP_A” TO “GRP_B” 5 ns DATAPATHONLY;
Constraints Guide
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