Xilinx Constraints Guide

HIODELAY_GROUP (HIODELAY Group)
Architecture Support
Applicable Elements
Propagation Rules
The HIODELAY_GROUP (HIODELAY Group) constraint:
• Is a design implementation constraint.
Chapter 4: Xilinx Constraints
• Groups a hierarchical set of IDELAY and IODELAYs with an IDELAYCTRL to enable
automatic replication and placement of IDELAYCTRL in a design.
For more information, see the IDELAYCTRL section of the device user guide.
Applies to Virtex®-4 and Virtex-5 devices. For Virtex-4 devices, HIODELAY_GROUP is
supported only when using the Timing Driven Pack and Placement Option in MAP.
IDELAY, IODELAY, and IDELAYCTRL primitive instantiations
HIODELAY_GROUP can be attached only to a design element. It is illegal to attach
HIODELAY_GROUP to a net, signal, or pin. To merge two or more embedded
HIODELAY_GROUP constraints in your design, see MIODELAY_GROUP (MIODELAY
Group).
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
VHDL Syntax
Declare the VHDL constraint as follows:
attribute HIODELAY_GROUP: string;
Specify the VHDL constraint as follows:
attribute HIODELAY_GROUP of {component_name|label_name}: {component|label} is
"group_name";
For a description of group_name, see UCF and NCF Syntax below.
For more information about basic VHDL syntax, see VHDL Attributes.
Verilog Syntax
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* HIODELAY_GROUP = "group_name" *)
For a description of group_name, see UCF and NCF Syntax below.
For more information about basic Verilog syntax, see Verilog Attributes.
UCF and NCF Syntax
INST "instance_name" HIODELAY_GROUP = group_name;
where
group_name is the name assigned to a set of IDELAY or IODELAY constraints and an
IDELAYCTRL to uniquely define the group.
Constraints Guide
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