Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
Open Drain (OPEN_DRAIN)
Architecture Support
Applicable Elements
CoolRunner-II outputs can be configured to drive the primary macrocell output
function as an open-drain output signal on the pin. Open Drain (OPEN_DRAIN) applies
to non tristate (always active) outputs in the design. The output structure is configured
as open-drain so that a one state on the output signal in the design produces a high-Z on
the device pin instead of a driven High voltage.
The high-Z behavior associated with OPEN_DRAIN is not exhibited during functional
simulation, but is represented accurately during post-fit timing simulation.
The logically-equivalent alternative to using OPEN_DRAIN is to take the original
output-pad signal in the design and use it as a tristate disable for a constant-zero
output data value. The CPLD Fitter automatically optimizes all tristate outputs with
constant-zero data value in the design to take advantage of the open-drain capability
of the device.
Applies to CoolRunner-II devices only.
• Output pads
• Pad nets
Propagation Rules
This constraint is a net or signal constraint. Any attachment to a macro, entity, or
module is illegal.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
• Attach to an output pad net
• Attribute Name
OPEN_DRAIN
• Attribute Values
– TRUE
– FALSE
VHDL Syntax
Declare the VHDL constraint as follows:
attribute OPEN_DRAIN: string;
Specify the VHDL constraint as follows:
attribute OPEN_DRAIN of signal_name : signal is “{TRUE|FALSE}”;
For more information about basic VHDL syntax, see VHDL Attributes.
Constraints Guide
204 www.xilinx.com UG625 (v. 13.2) July 6, 2011