Xilinx Constraints Guide

BUFG (BUFG)
The BUFG (BUFG) constraint:
• Is an advanced fitter constraint.
• Is a synthesis constraint.
Chapter 4: Xilinx Constraints
When applied to an input buffer or input pad net, BUFG maps the tagged signal to a
global net. When applied to an internal net, the tagged signal is either routed directly to
a global net or brought out to a global control pin to drive the global net, as supported
by the target device family architecture.
• CLK
• OE
• SR
Maps to a global clock (GCK) line
Maps to a global tristate control (GTS) line
Maps to a global set/reset control (GSR) line
• DATA_GATE
Architecture Support
Applicable Elements
Propagation Rules
Maps to the DATA_GATE latch enable control line
Applies to CPLD devices only. Does not apply to FPGA devices.
Any input buffer (IBUF), input pad net, or internal net that drives a CLK, OE, SR, or
DATA_GATE pin
When attached to a net, BUFG has a net or signal form and so no special propagation
is required. When attached to a design element, BUFG is propagated to all applicable
elements in the hierarchy within the design element.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
• Attach to an IBUF instance of the input pad connected to an IBUF input
• Attribute Name
BUFG
VHDL Syntax
Declare the VHDL constraint as follows:
attribute BUFG: string;
Specify the VHDL constraint as follows:
attribute BUFG of signal_name : signal is “{CLK|OE |SR|DATA_GATE} ”;
For more information about basic VHDL syntax, see VHDL Attributes.
Constraints Guide
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