Xilinx Constraints Guide

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Chapter 4: Xilinx Constraints Separating Elements from H_SET Sets The HU_SET (HU Set) constraint is a variation of the implicit H_SET (hierarchy set). HU_SET defines the start of a new set. Like H_SET, HU_SET is defined by the design hierarchy. However, you can use HU_SET to assign a user-defined name to the HU_SET. This example demonstrates how HU_SET constraints designate elements as set members, break links between elements tagged with RLOC constraints in the hierarchy to separate them from H_SET sets, and generate names as identifiers of these sets. The user-defined HU_SET constraint on E separates its underlying design elements, namely H, I, J, K, L, and M from the implicit H_SET=A/h_set that contains primitive members B, C, F, and G. The HU_SET set that is defined at E includes H, I, and L (through the element J). The mapper hierarchically qualifies the name value “bar” on element E to be A/bar, since A is the lowest common ancestor for all the elements of the HU_SET set, and attaches it to the set member primitives H, I, and L. An HU_SET constraint on K starts another set that includes M, which receives the HU_SET=A/E/bar constraint after processing by the mapper. The same name field is used for the two HU_SET constraints, but because they are attached to symbols at different levels of the hierarchy, they define two different sets. Constraints Guide 242 www.xilinx.com UG625 (v. 13.2) July 6, 2011
Linking Two HU_SET Sets Chapter 4: Xilinx Constraints This example shows how HU_SET constraints link elements in the same node together by naming them with the same identifier. Because of the same name (bar) on two elements, D and E, the elements tagged with RLOC constraints below D and E become part of the same HU_SET. Constraints Guide UG625 (v. 13.2) July 6, 2011 www.xilinx.com 243
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Constraints Guide UG625 (v. 13.2) J
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Table of Contents Revision History
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IBUF_DELAY_VALUE (Input Buffer Dela
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Constraint Types Attributes and Con
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Grouping Constraints for Timing Cha
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The name qualifier can include the
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Physical Constraints Mapping Note T
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Placement Constraints Chapter 1: Co
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Routing Directives Routing directiv
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Timing Constraints Chapter 1: Const
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UCF Timing Constraint Support From-
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Timing Model Constraint Priority Ch
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Chapter 2 Entry Strategies for Xili
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Constraint Schematic VHDL Verilog L
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An attribute can be declared in an
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User Constraints File (UCF) UCF Flo
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Syntax Chapter 2: Entry Strategies
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Entering Multiple Constraints File
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Chapter 2: Entry Strategies for Xil
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Running Constraints Editor As a Sta
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Defining I/O Pin Configurations Cha
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Placement LOC Constraint Assignment
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Verilog Example -------------module
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Chapter 2: Entry Strategies for Xil
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Timing Specification Priorities Cha
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Timing Constraint Strategies Chapte
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Chapter 3: Timing Constraint Strate
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The global OFFSET IN constraint for
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The PERIOD constraint syntax for th
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Example Chapter 3: Timing Constrain
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Chapter 3: Timing Constraint Strate
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The global OFFSET OUT constraints f
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Multi-Cycle Paths Chapter 3: Timing
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Xilinx Constraints Each Xilinx® co
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RANGE Chapter 4: Xilinx Constraints
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Chapter 4: Xilinx Constraints Range
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COMPRESSION GROUP PLACE Chapter 4:
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Defining From Timing Groups Chapter
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BEL (BEL) The BEL (BEL) constraint:
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BLKNM (Block Name) Architecture Sup
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BUFG (BUFG) The BUFG (BUFG) constra
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Clock Dedicated Route (CLOCK_DEDICA
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COMPGRP (Component Group) Architect
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• S_SELECTMAP16 Slave SelectMAP M
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Verilog Syntax Chapter 4: Xilinx Co
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PCF Syntax CONFIG DCI_CASCADE = ",
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Default (DEFAULT) Chapter 4: Xilinx
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Example (* KEEPER = “TRUE” *) D
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DIFF_TERM (Diff_Term) Architecture
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DIRECTED_ROUTING (Directed Routing)
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DISABLE (Disable) The DISABLE (Disa
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DRIVE (Drive) The DRIVE (Drive) con
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XCF Syntax MODEL “entity_name”
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ENABLE (Enable) The ENABLE (Enable)
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ENABLE_SUSPEND (Enable Suspend) Arc
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Constraints Editor Syntax Chapter 4
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VHDL Syntax Declare the VHDL constr
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UCF and NCF Syntax NET “signal_na
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Chapter 4: Xilinx Constraints You a
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Constraints Editor Syntax Chapter 4
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HBLKNM (Hierarchical Block Name) Ar
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HIODELAY_GROUP (HIODELAY Group) Arc
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HU_SET (HU Set) The HU_SET (HU Set)
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IBUF_DELAY_VALUE (Input Buffer Dela
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IFD_DELAY_VALUE (IFD Delay Value) T
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IN_TERM (In Term) Architecture Supp
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INREG (Input Registers) Architectur
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IOB (IOB) The IOB constraint: • I
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IOBDELAY (Input Output Block Delay)
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IODELAY_GROUP (IODELAY Group) Limit
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IOSTANDARD (Input Output Standard)
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Pinout and Area Constraints Editor
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Architecture Support Applicable Ele
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Keeper (KEEPER) Architecture Suppor
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LOC (Location) The LOC (Location) c
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Chapter 4: Xilinx Constraints The w
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LOC Range Constraint Examples Const
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PlanAhead Syntax Chapter 4: Xilinx
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Schematic LOC=P17 Chapter 4: Xilinx
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Example One Chapter 4: Xilinx Const
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Slices Prohibited Example Two Chapt
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LOCK_PINS (Lock Pins) Architecture
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where value is any chosen name unde
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MAP (Map) Architecture Support Appl
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Specify the Verilog constraint as f
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Architecture Support Applicable Ele
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MAXDELAY (Maximum Delay) Architectu
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PCF Syntax item MAXDELAY = maxvalue
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MAXSKEW (Maximum Skew) The MAXSKEW
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FPGA Editor Syntax Chapter 4: Xilin
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MIODELAY_GROUP (MIODELAY Group) Arc
Page 191 and 192: VHDL Syntax Declare the VHDL constr
Page 193 and 194: UCF and NCF Syntax Chapter 4: Xilin
Page 195 and 196: where Chapter 4: Xilinx Constraints
Page 197 and 198: Falling Edge Constraints Chapter 4:
Page 199 and 200: PlanAhead Syntax Chapter 4: Xilinx
Page 201 and 202: where Chapter 4: Xilinx Constraints
Page 203 and 204: UCF Syntax NET “clock” TNM_NET
Page 205 and 206: Verilog Syntax Chapter 4: Xilinx Co
Page 207 and 208: Attribute OUT_TERM: string; Specify
Page 209 and 210: TIMESPEC PERIOD Method Chapter 4: X
Page 211 and 212: Examples of a Primary Clock with De
Page 213 and 214: where • period is the required cl
Page 215 and 216: New PERIOD Specifications Output Pi
Page 217 and 218: Post CRC (POST_CRC) Architecture Su
Page 219 and 220: Post CRC Frequency (POST_CRC_FREQ)
Page 221 and 222: Post CRC Signal (POST_CRC_SIGNAL) A
Page 223 and 224: PRIORITY (Priority) Architecture Su
Page 225 and 226: The following are not supported: Ch
Page 227 and 228: PULLDOWN (Pulldown) Architecture Su
Page 229 and 230: PULLUP (Pullup) Architecture Suppor
Page 231 and 232: PWR_MODE (Power Mode) Architecture
Page 233 and 234: REG (Registers) The REG (Registers)
Page 235 and 236: RLOC (Relative Location) The Relati
Page 237 and 238: RLOC = X3Y4 Chapter 4: Xilinx Const
Page 239 and 240: Linking Sets Set Linkage Chapter 4:
Page 241: Chapter 4: Xilinx Constraints by th
Page 245 and 246: Specify the VHDL constraint as foll
Page 247 and 248: Chapter 4: Xilinx Constraints Diffe
Page 249 and 250: H_SET (H Set) Chapter 4: Xilinx Con
Page 251 and 252: Chapter 4: Xilinx Constraints The n
Page 253 and 254: Syntax Examples Chapter 4: Xilinx C
Page 255 and 256: RLOC_RANGE (Relative Location Range
Page 257 and 258: where the relative X values (m1 and
Page 259 and 260: VHDL Syntax Declare the VHDL constr
Page 261 and 262: UCF and NCF Syntax NET “mysignal
Page 265 and 266: VHDL Syntax Chapter 4: Xilinx Const
Page 267 and 268: SLOW (Slow) The SLOW (Slow) constra
Page 269 and 270: STEPPING (Stepping) Architecture Su
Page 271 and 272: VHDL Syntax Chapter 4: Xilinx Const
Page 275 and 276: Constraints Editor Syntax Chapter 4
Page 277 and 278: Chapter 4: Xilinx Constraints The f
Page 279 and 280: TIMEGRP (Timing Group) The TIMEGRP
Page 281 and 282: Defining Latch Subgroups by Gate Se
Page 283 and 284: Chapter 4: Xilinx Constraints When
Page 285 and 286: PCF Syntax TIMEGRP name; TIMEGRP na
Page 287 and 288: Separators FROM-TO Syntax TIMESPEC
Page 289 and 290: TNM (Timing Name) Chapter 4: Xilinx
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TNM_NET (Timing Name Net) The TNM_N
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Schematic Syntax • Attach to a ne
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TPSYNC (Timing Point Synchronizatio
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UCF and NCF Syntax NET “net_name
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Using TPTHRU in a FROM TO Constrain
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TSidentifier (Timing Specification
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Ignoring Paths Note This form is no
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UCF and NCF Syntax Chapter 4: Xilin
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Chapter 4: Xilinx Constraints If yo
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Use Low Skew Lines (USELOWSKEWLINES
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VCCAUX (VCCAUX) Architecture Suppor
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UCF and NCF Syntax Chapter 4: Xilin
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VREF (VREF) The VREF (VREF) constra
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XBLKNM (XBLKNM) Architecture Suppor
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Additional Resources Appendix • X
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