Xilinx Constraints Guide

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Chapter 4: Xilinx Constraints The following statement identifies all flip-flops fanning out from the PADCLK net as a member of the timing group GRP1. NET “PADCLK” TNM_NET=FFS ”GRP1”; XCF Syntax XST supports TNM_NET with the following limitation: only a single pattern supported for predefined groups. The following command syntax is supported: NET “PADCLK” TNM_NET=FFS ”GRP1”; The following command syntax is not supported: NET “PADCLK” TNM_NET = FFS(machine/*:xcounter/*) TG1; Constraints Editor Syntax For information on setting constraints in Constraints Editor, including syntax, see the Constraints Editor Help. PlanAhead Syntax For more information about using the PlanAhead software to create constraints, see Floorplanning the Design in the PlanAhead User Guide (UG632). See PlanAhead in this Guide for information about: • Defining placement constraints • Assigning placement constraints • Defining I/O pin configurations • Floorplanning and placement constraints Constraints Guide 296 www.xilinx.com UG625 (v. 13.2) July 6, 2011
TPSYNC (Timing Point Synchronization) The TPSYNC (Timing Point Synchronization) constraint: • Is a grouping constraint. Architecture Support Applicable Elements Chapter 4: Xilinx Constraints • Flags a particular point or a set of points with an identifier for use in subsequent timing specifications. If you use the same identifier on several points, timing analysis treats the points as a group Applies to FPGA devices. Does not apply to CPLD devices. • Nets • Instances • Pins Propagation Rules When the timing of a design must be designed from or to a point that is not a synchronous element or I/O pad, the following rules apply if a TPSYNC timing point is attached to any of the following. • Net The source of the net is identified as a potential source or destination for timing specifications. • Macro pin All of the sources inside the macro that drive the pin to which the constraint is attached are identified as potential sources or destinations for timing specifications. If the macro pin is an input pin (that is, if there are no sources for the pin in the macro), then all of the load pins in the macro are flagged as synchronous points. • The output pin of a primitive The output is flagged as a potential source or destination for timing specifications. • The input pin of a primitive The input of the primitive is flagged as a potential source or destination for timing specifications. • An instance The output of that element is identified as a potential source or destination for timing specifications. • A primitive symbol Attached to a primitive symbol, TPSYNC identifies the outputs of that element as a potential source or destination for timing specifications. See the following figure. Constraints Guide UG625 (v. 13.2) July 6, 2011 www.xilinx.com 297
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Constraints Guide UG625 (v. 13.2) J
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Table of Contents Revision History
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IBUF_DELAY_VALUE (Input Buffer Dela
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Constraint Types Attributes and Con
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Grouping Constraints for Timing Cha
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The name qualifier can include the
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Physical Constraints Mapping Note T
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Placement Constraints Chapter 1: Co
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Routing Directives Routing directiv
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Timing Constraints Chapter 1: Const
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UCF Timing Constraint Support From-
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Timing Model Constraint Priority Ch
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Chapter 2 Entry Strategies for Xili
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Constraint Schematic VHDL Verilog L
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An attribute can be declared in an
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User Constraints File (UCF) UCF Flo
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Syntax Chapter 2: Entry Strategies
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Entering Multiple Constraints File
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Chapter 2: Entry Strategies for Xil
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Running Constraints Editor As a Sta
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Defining I/O Pin Configurations Cha
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Placement LOC Constraint Assignment
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Verilog Example -------------module
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Chapter 2: Entry Strategies for Xil
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Timing Specification Priorities Cha
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Timing Constraint Strategies Chapte
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Chapter 3: Timing Constraint Strate
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The global OFFSET IN constraint for
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The PERIOD constraint syntax for th
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Example Chapter 3: Timing Constrain
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Chapter 3: Timing Constraint Strate
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The global OFFSET OUT constraints f
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Multi-Cycle Paths Chapter 3: Timing
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Xilinx Constraints Each Xilinx® co
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RANGE Chapter 4: Xilinx Constraints
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Chapter 4: Xilinx Constraints Range
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COMPRESSION GROUP PLACE Chapter 4:
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Defining From Timing Groups Chapter
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BEL (BEL) The BEL (BEL) constraint:
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BLKNM (Block Name) Architecture Sup
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BUFG (BUFG) The BUFG (BUFG) constra
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Clock Dedicated Route (CLOCK_DEDICA
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COMPGRP (Component Group) Architect
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• S_SELECTMAP16 Slave SelectMAP M
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Verilog Syntax Chapter 4: Xilinx Co
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PCF Syntax CONFIG DCI_CASCADE = ",
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Default (DEFAULT) Chapter 4: Xilinx
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Example (* KEEPER = “TRUE” *) D
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DIFF_TERM (Diff_Term) Architecture
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DIRECTED_ROUTING (Directed Routing)
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DISABLE (Disable) The DISABLE (Disa
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DRIVE (Drive) The DRIVE (Drive) con
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XCF Syntax MODEL “entity_name”
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ENABLE (Enable) The ENABLE (Enable)
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ENABLE_SUSPEND (Enable Suspend) Arc
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Constraints Editor Syntax Chapter 4
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VHDL Syntax Declare the VHDL constr
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UCF and NCF Syntax NET “signal_na
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Chapter 4: Xilinx Constraints You a
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Constraints Editor Syntax Chapter 4
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HBLKNM (Hierarchical Block Name) Ar
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HIODELAY_GROUP (HIODELAY Group) Arc
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HU_SET (HU Set) The HU_SET (HU Set)
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IBUF_DELAY_VALUE (Input Buffer Dela
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IFD_DELAY_VALUE (IFD Delay Value) T
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IN_TERM (In Term) Architecture Supp
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INREG (Input Registers) Architectur
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IOB (IOB) The IOB constraint: • I
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IOBDELAY (Input Output Block Delay)
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IODELAY_GROUP (IODELAY Group) Limit
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IOSTANDARD (Input Output Standard)
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Pinout and Area Constraints Editor
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Architecture Support Applicable Ele
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Keeper (KEEPER) Architecture Suppor
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LOC (Location) The LOC (Location) c
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Chapter 4: Xilinx Constraints The w
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LOC Range Constraint Examples Const
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PlanAhead Syntax Chapter 4: Xilinx
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Schematic LOC=P17 Chapter 4: Xilinx
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Example One Chapter 4: Xilinx Const
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Slices Prohibited Example Two Chapt
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LOCK_PINS (Lock Pins) Architecture
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where value is any chosen name unde
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MAP (Map) Architecture Support Appl
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Specify the Verilog constraint as f
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Architecture Support Applicable Ele
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MAXDELAY (Maximum Delay) Architectu
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PCF Syntax item MAXDELAY = maxvalue
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MAXSKEW (Maximum Skew) The MAXSKEW
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FPGA Editor Syntax Chapter 4: Xilin
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MIODELAY_GROUP (MIODELAY Group) Arc
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UCF and NCF Syntax Chapter 4: Xilin
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where Chapter 4: Xilinx Constraints
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Falling Edge Constraints Chapter 4:
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PlanAhead Syntax Chapter 4: Xilinx
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where Chapter 4: Xilinx Constraints
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UCF Syntax NET “clock” TNM_NET
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Attribute OUT_TERM: string; Specify
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TIMESPEC PERIOD Method Chapter 4: X
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Examples of a Primary Clock with De
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where • period is the required cl
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New PERIOD Specifications Output Pi
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Post CRC (POST_CRC) Architecture Su
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Post CRC Frequency (POST_CRC_FREQ)
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Post CRC Signal (POST_CRC_SIGNAL) A
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PRIORITY (Priority) Architecture Su
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The following are not supported: Ch
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PULLDOWN (Pulldown) Architecture Su
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PULLUP (Pullup) Architecture Suppor
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PWR_MODE (Power Mode) Architecture
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REG (Registers) The REG (Registers)
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RLOC (Relative Location) The Relati
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RLOC = X3Y4 Chapter 4: Xilinx Const
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Linking Sets Set Linkage Chapter 4:
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Chapter 4: Xilinx Constraints by th
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Linking Two HU_SET Sets Chapter 4:
Page 245 and 246: Specify the VHDL constraint as foll
Page 247 and 248: Chapter 4: Xilinx Constraints Diffe
Page 249 and 250: H_SET (H Set) Chapter 4: Xilinx Con
Page 251 and 252: Chapter 4: Xilinx Constraints The n
Page 253 and 254: Syntax Examples Chapter 4: Xilinx C
Page 255 and 256: RLOC_RANGE (Relative Location Range
Page 257 and 258: where the relative X values (m1 and
Page 259 and 260: VHDL Syntax Declare the VHDL constr
Page 261 and 262: UCF and NCF Syntax NET “mysignal
Page 263 and 264: Verilog Syntax Chapter 4: Xilinx Co
Page 265 and 266: VHDL Syntax Chapter 4: Xilinx Const
Page 267 and 268: SLOW (Slow) The SLOW (Slow) constra
Page 269 and 270: STEPPING (Stepping) Architecture Su
Page 271 and 272: VHDL Syntax Chapter 4: Xilinx Const
Page 275 and 276: Constraints Editor Syntax Chapter 4
Page 277 and 278: Chapter 4: Xilinx Constraints The f
Page 279 and 280: TIMEGRP (Timing Group) The TIMEGRP
Page 281 and 282: Defining Latch Subgroups by Gate Se
Page 283 and 284: Chapter 4: Xilinx Constraints When
Page 285 and 286: PCF Syntax TIMEGRP name; TIMEGRP na
Page 287 and 288: Separators FROM-TO Syntax TIMESPEC
Page 289 and 290: TNM (Timing Name) Chapter 4: Xilinx
Page 291 and 292: Chapter 4: Xilinx Constraints A qua
Page 293 and 294: TNM_NET (Timing Name Net) The TNM_N
Page 295: Schematic Syntax • Attach to a ne
Page 299 and 300: UCF and NCF Syntax NET “net_name
Page 301 and 302: Using TPTHRU in a FROM TO Constrain
Page 303 and 304: TSidentifier (Timing Specification
Page 305 and 306: Ignoring Paths Note This form is no
Page 307 and 308: VHDL Syntax Declare the VHDL constr
Page 309 and 310: UCF and NCF Syntax Chapter 4: Xilin
Page 313 and 314: Chapter 4: Xilinx Constraints If yo
Page 315 and 316: Use Low Skew Lines (USELOWSKEWLINES
Page 317 and 318: VCCAUX (VCCAUX) Architecture Suppor
Page 319 and 320: UCF and NCF Syntax Chapter 4: Xilin
Page 321 and 322: VREF (VREF) The VREF (VREF) constra
Page 323 and 324: XBLKNM (XBLKNM) Architecture Suppor
Page 325: Additional Resources Appendix • X
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