Xilinx Constraints Guide

Chapter 2
Entry Strategies for Xilinx Constraints
Constraints Entry Methods
This chapter discusses entry strategies for Xilinx® constraints, including how to use
ISE® Design Suite to enter a given constraint type.
The following table shows which feature of ISE® Design Suite to use to enter a given
constraint type.
Constraints Entry Methods
Constraint Type Tool Devices
Timing Constraints Editor All CPLD and FPGA device
families
IO placement and area-group
constraints
PlanAhead Software All FPGA device families
IO placement PACE All CPLD device families
IO placement and other
placement constraints
Constraints Entry Table
Constraint Schematic
Schematic and Symbol Editors All CPLD and FPGA device
families
The following table lists the constraints and their associated entry strategies. See the
individual constraint for syntax examples.
Constraints Entry Table
VHDL
Verilog
NCF UCF Constraints
Editor
PCF XCF Plan-
Ahead
AREA_GROUP Yes Yes Yes Yes Yes
ASYNC_REG Yes Yes Yes Yes
BEL Yes Yes Yes Yes
BLKNM Yes Yes Yes Yes Yes
BUFG (CPLD) Yes Yes Yes Yes Yes
CLOCK_DEDICATED
_ROUTE
Yes Yes
COLLAPSE Yes Yes Yes Yes
COMPGRP Yes
PACE FPGA
Editor
ISE®
Design
Suite
Constraints Guide
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