Xilinx Constraints Guide

Chapter 1: Constraint Types
Logical Constraints
Logical constraints are constraints that are attached to elements before mapping or
fitting.
• Logical constraints help adapt design performance to expected worst-case
conditions.
• Logical constraints are converted into physical constraints when you:
1. Choose a specific Xilinx® architecture, and
2. Place and Route, or fit, the design.
• You can attach logical constraints using attributes in the input design, which
are written into the Netlist Constraints File (NCF) or NGC netlist, or with a User
Constraints File (UCF).
• Three categories of logical constraints are:
– Placement Constraints
– Relative Location Constraints
For FPGA devices, Relative Location constraints:
♦ Group logic elements into discrete sets.
♦ Allow you to define the location of any element within the set relative to
other elements in the set, regardless of eventual placement in the overall
design.
– Timing Constraints
Timing constraints allow you to specify the maximum allowable delay or skew
on any given set of paths or nets.
Constraints Guide
12 www.xilinx.com UG625 (v. 13.2) July 6, 2011