Xilinx Constraints Guide

VHDL Syntax
Declare the VHDL constraint as follows:
attribute U_SET: string;
Specify the VHDL constraint as follows:
Chapter 4: Xilinx Constraints
attribute U_SET of {component_name |label_name}: {component|label} is name;
where
name is the identifier of the set
For more information about basic VHDL syntax, see VHDL Attributes.
Verilog Syntax
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* U_SET = name *)
where
name is the identifier of the set
For more information about basic Verilog syntax, see Verilog Attributes.
UCF and NCF Syntax
INST "instance_name" U_SET= name;
where
name is the identifier of the set
This name is absolute. It is not prefixed by a hierarchical qualifier.
The following statement specifies that the design element ELEM_1 be in a set called
JET_SET.
INST "$1I3245/ELEM_1" U_SET=JET_SET;
XCF Syntax
BEGIN MODEL entity_name
INST "instance_name" U_SET=uset_name;
END;
Constraints Guide
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