Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
LOCATE (Locate)
The LOCATE (Locate) constraint:
• Is a basic placement constraint.
• Specifies any one of the following:
– a single location
– multiple single locations
– a location range
Architecture Support
Applicable Elements
Applies to FPGA devices. Does not apply to CPLD devices.
• CLB
• IOB
• DCM
• Clock logic
• Macros
Propagation Rules
• When attached to a macro, LOCATE propagates to all elements of the macro.
• When attached to a primitive, LOCATE applies to the entire primitive.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Single or Multiple Single Locations PCF Syntax
COMP “comp_name” LOCATE=[SOFT] “site_item1”... “site_itemn” [LEVEL n];
COMPGRP “group_name” LOCATE=[SOFT] “site_item1”... “site_itemn” [LEVEL n];
MACRO name LOCATE=[SOFT] “site_item1” “site_itemn” [LEVEL n];
Range of Locations PCF Syntax
COMP “comp_name” LOCATE=[SOFT] SITE “site_name” : SITE “site_name” [LEVEL n];
COMPGRP “group_name” LOCATE=[SOFT] SITE “site_name” : SITE “site_name”
[LEVEL n];
MACRO “macro_name” LOCATE=[SOFT] SITE “site_name” : SITE “site_name” [LEVEL
n];
where
• site_name is a component site (that is, a CLB or IOB location)
• site_item is one of the following:
– SITE "site_name"
– SITEGRP "site_group_name"
• n in LEVEL n is 0, 1, 2, 3, or 4
Constraints Guide
170 www.xilinx.com UG625 (v. 13.2) July 6, 2011